Got a question.
I'm using an Aria V, DDR2 SDRAM Controller with UniPHY, running the controller in Hard External Memory Interface. My memory clock is 400MHz and data width is 32-bits (since its double data rate this can be thought of as 64-bits at 400MHz). The Avalon-MM interface is set to "Full", which is the only option for Aria V, Hard. This gives an Avalon-MM bus width of 64-bits.
But.....The documentation, as well as my experimentation, says that the controller logic will only run at a maximum of 1/2 the memory interface clock, so that's 200MHz in my case.
This results in an effective memory bandwidth of 1/2 what the memory can achieve.
I've tried setting the port data width to 128-bits, but the interface doesn't seem to work with that setting. And this seems to be an illegal setting.
I've tried taking a 128-bit bus, splitting it into two 64 bit busses, and then running them into two ports on the controller. I then set the address MSB of one port to "1" and the second to "0". But it doesn't appear to truly be doing the two ports at once, just bouncing between them. This seems correct given the different address.
so am I missing something? Can the controller IP not give full memory data rates when using the Hard External Memory Interface option?
