Arria 10: Connect TSE IP to RGMII PHY

[MathiasB]

Hello all,

I am working on a board embedding a Arria 10 SX SoC, connected to an Ethernet PHY.

I would like to use the Triple Speed Ethernet (TSE) IP with this PHY. However, its interface is RGMII and I have found that Arria 10 does not allow RGMII <-> TSE connection (from Intel KDB: https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/ip/2017/does-the-triple-speed-ethernet-ip-core-support-rgmii-mode-in-a10.html)

Is there a known solution to circumvent this problem? Whether it is by instantiating a bridge IP, replacing the TSE by something else or using the HPS as some kind of bridge?

Thank you!

[Deshi_Intel · Accepted solution]

HI,

Unfortunately this is Arria 10 device architecture limitation when interacting with RGMII PHY interface.

The limitation is on the data transfer path between FPGA IO circuitry block to FPGA core logic (where soft IP solution is located like TSE)

Therefore, Unfortunately there is no solution for it.

Thanks for your understanding

Regards,

dlim

[MathiasB]

Thank you for your answer.

Does that mean that I have to use the HPS to interface the Arria 10 to a RGMII Ethernet PHY?

This at least should be possible, based on https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_5v4.pdf §18.1.5

[Deshi_Intel]

HI,

I am not familiar with HPS system but looks like you are right.

It seem to be possible to interact with RGMII interface if using HPS EMAC

You can refer to below link (page 46, chapter 4.5.1 HPS EMAC PHY Interfaces)

• https://www.intel.cn/content/dam/www/programmable/us/en/pdfs/literature/an/an-a10-soc-device-design-guidelines.pdf

Thanks.

Regards,

dlim

[MathiasB]

Hi,

In the end, we are not going to use the RGMII Phy on the board. The system provides us an other Ethernet interface which wa can use as SGMII.

Thank you for your help, I accept your firt answer as solution.

[Deshi_Intel]

alright, noted