I have generated an Altera PLL using Quartus Prime Standard Edition 17.1. The PLL accepts a 50 MHz reference clock, and produces five output clocks: 50 MHz, 200 MHz, 200 MHz w/ 1250ps shift, 333 MHz, and 333 MHz w/ 750ps shift.
The IP generator GUI tells me all user settings are accepted as-is (i.e. the actual phase shifts and clock frequencies are possible and won't be changed). However when I simulate the PLL, all clocks are correct except for the 200 MHz with 1250ps phase shift, the phase shift is only 250ps.
I double-checked my settings in the GUI, and even visually inspected the generics in the generated synthesis and simulation files. I can't figure out why it won't simulate correctly, is this perhaps a tool bug? Something I did wrong? I'm worried that if it simulates this way, it could function that way in hardware as well and I need the 90 degree phase shift for proper operation. Thanks for any help!
Currently I am reviewing the forum for any open questions and found this thread. I apologize that no one seems to answer this question that you posted. Since it has been a while you posted this question, I'm wondering if you have found the answer? If not, please let me know, I will try to assign/find someone to assist you. Thank you.
Hi Nooraini! Thanks for the reply, unfortunately I have not resolved this issue yet. In simulation the phase shift of that one clock is still incorrect.
The silver lining is that my design is functioning properly in hardware, however I do not have the measurement equipment necessary for accurate measurement of two 200 MHz clocks to see if the synthesized design is producing the correct phase shift. It is possible it is correct in synthesis and this is a simulation-only problem, or it is possible that my design just happens to work regardless, and I can't be sure which.
If you could find an Intel resource to investigate this I would appreciate it. I attached the IP output in the original post, hopefully that can be used to help. Please let me know if I can provide any additional information.
My simulator is ModelSim - Intel FPGA Edition 10.5b
I am asked to look into your case and see if there is anything i can help out . May I know what does the fitter report says, does it show the correct phase shift?
Meanwhile, let me check the simulation with the 18.1 and Modelsim 10.5c. If the latest works fine, would you be able to check with the latest versions as well?
Tested on QII v18.1std and Modelsim 10.6d.
It seemed to work fine.
I used your Qsys file, wrap it with a top file, recompiled and simulated it. I attached the folder.
To simulate, open up Modelsim. Go to <unzipped path>/simulation/modelsim
Run: do pllforum_run_msim_rtl_verilog.do
It should show as screenshot.
You will see outclk3 and outclk4 are shifted by 1250ps as expected.
Very interesting, and thank you again for your time and assistance. I downloaded your .zip file, I had to modify a couple of file paths that had absolute directory paths for your local work area. But once that was fixed, the simulation runs though for me it still shows the wrong phase shift! I've attached the screenshot of my simulator. I am still using the older version of ModelSim. I will attempt to update to a newer version and see if that change alone fixes the problem.
I think based on your newer simulator version showing it working, along with my hardware functioning properly and reliably, it is safe to assume this is a simulation-only problem that I can ignore. It is good to know it seems to be version-specific (lucky me!). Thank you again for your help, once I'm able to try with a newer version I'll update this thread as well to confirm that I see proper operation as well.