I am in the early stages of my design working on Schematic verification. I am working on Arria 10 SoC 10AS066K2F40E1HG in Quartus Prime Pro 17.1
my design contains a high speed ADC which gives LVDS serialized output. I need to verify the IO banks and the pins assigned to the ADC (ucf) to ensure that my logic will fit in the banks.
For this purpose, I am using LVDS Serdes IP which takes the differential pins of the ADC as input. I am using Alt_INBUF_DIFF primitive for feeding the input to SERDES IP. Outputs of the Serdes IP are further fed to a FIFO, and further to UART IP to get the data out of the FPGA. This is done to prevent optimization of the SERDES IP.
The Serdes IP example design requires clocks as inputs. When I connect my differential system clock to the Qsys generated template, I get the below error--
Output Port RXDATA on atom "<LVDS_example_IP_name>", which is a twentynm_io_serdes_dpa primitive, is not legally connected and/or configured.
Any suggestions to the error?
Thanks in Advance.
First of all, I think you do not need to use Alt_INBUF_DIFF primitive and can directly connect input ports from ADC to SERDES IP.
As about clocks, you'd better attach a project, but for now I can say that maybe you used not dedicated clock pin as input to LVDS SERDES.
Hi @IDeyn ,
The outputs of my ADC (partno: ADS42LB69) are differential. the template instantiation in VHDL requires std_logic_vector as input where each bit corresponds to 1 bit (P and N together make 1 bit, correct me if I am wrong). So I couldn't find a way to directly connect differential pins of the ADC to the SERDES IP. Hence, I have used Alt_INBUF_DIFF.
Also, regarding clock, I am feeding the output clock from the ADC to the SERDES IP. My design fails in the synthesis stage itself. So I believe the issue is in the code somewhere rather than pin assignment. anyways, you can still check the pin planner, assigned pins are clock capable.
Have a look at my attached project.
Thanks in Advance.
After brief look at your project, I can say that you need to change SERDES factor to 8, because your ADC is 16-bit wide. Update - you need to change that in ... LVDS_example_IP_name ...
For further work, you'd check this video - https://www.youtube.com/watch?v=02lgfcxSjQA
Of course, this video explains 14-bit case, in your case you need 16-bit.
And as about connection of differential ports - I think you could directly connect input P pin to ALTLVDS SERDES without any issues.
Hi @IDeyn ,
with your suggestions, I was able to solve the error.
In my schematic, I have a total of 8 ICs of my ADC. So total of 16 channels are mapped. In 1 IO bank, total 4 channels of 2 ADCs are mapped . When I try to generate the design with 2 SERDES IPs in the same bank, the fitter is unable to fit the design. My question is will one bank support only 1 SERDES at max?
Also, If i want to map the clock from ADC to a non-clock pin, is it possible to force the fitter to accept the assignment by constraints?
Attached is my updated project.
I'm unable to inspect your updated project at this week - I'm not at home.
So first of all it is great that you were able to solve the error.
I will return and see our project.
As about your new questions.
I suppose that one bank could support more than 1 SERDES, but I need to check your particular case.
As about mapping a clock to non-dedicated clokc pin - it is a bad idea and you better avoid doing this,
in that case SERDES IP couldn't be able to use PLL to compensate for a phase difference between clock and data.
I've just downloaded and inspected your project.
You see that error message:
"Error(18805): No dedicated path available for refclk signal, FMC3_ADC5_DACLK_P. Please promote your refclk to a global clock or move it to a dedicated IOPLL refclk pin. (1 location affected) "
You have to replace PIN_AK10 to a dedicated clock pin, because you want to use PLL and PLL's clock input need to be driven by dedicated clock input.
You can see that inside the bank there is another didicated clock pair - pins AU7-AT7 - you have to choose them instead.
Hope that helps.