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Arria10 SoC FPGAのボードデザイン・ガイドラインの5.5.1.1.2 RGMⅡにある、
「送信パスのセットアップ/ホールド
TX_CTL と TXD[3:0]への TX_CLK のセットアップとホールドだけが送信に関係します。 Arria10 I/O は、最大 800ps の出力遅延を提供できます。この遅延は、Quartus Prime のアサインメント・エディター内の出力遅延ロジックオプションを使用して有効になります。」とあるのですが、Quartus Primeでの設定方法を教えて頂けないでしょうか。
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Hi,
May I know which Quartus Prime Version are you working on?
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返信ありがとうございます。
Quartus Prime Version は16.1 Standard Editionを使用してます。
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Hi,
You may set the delay output in Assignment Editor, using Output Delay Chain Setting.
Please refer to our Arria 10 datasheet below:
https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/arria-10/a10_datasheet.pdf#page=64
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Hi,
I hope above answers your initial questions.
Do you have any additional questions?
Thanks!
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