Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16824 Discussions

Assistance for HPS and MSGDMA IP for Agilex 7

Balkesh
Beginner
464 Views

Hi all,

I am new to working with HPS so I want some assistance regarding these and I am using Agilex 7 board:

1) Actually I am using HPS with MSGDMA IP so can we simulate the project in modelsim as the board is not available right now and if possible can you provide the steps for the above process as I am not finding any documentation related to the same

2) .c and .h file for MSGDMA IP how they are compiled in the project or utilized

3) I have download Intel SoCEDS and ARM DS i want to ask what is the main purpose of these tools for HPS 

4) I also following a project related to communication between HPS and MSGDMA using Cyclone V board in that there is one dts file as well i want to know what is the purpose of this file, like it is the file for HPS OS or it is also in modelsim simulation

0 Kudos
5 Replies
aikeu
Employee
336 Views

Hi Balkesh,


For msgdma IP, you can refer to the below two design examples which may help:

Involves Nios processor only:

https://www.intel.com/content/www/us/en/design-example/790774/agilex-7-fpga-nios-v-m-processor-with-ddr-dma-and-ocm-design-example.html

Involves Nios processor and HPS:

https://www.rocketboards.org/foswiki/Projects/Datamover


ARM DS is meant for debugging purpose. SoC EDS is a discontinued product, which is no longer supported. Anyway the information can used as your reference:

https://www.rocketboards.org/foswiki/Documentation/SoCEDS


You can refer to the link below for simulation related with Nios:

https://www.intel.com/content/www/us/en/docs/programmable/726952/22-1-21-2-0/simulating-processor-designs.html


Thanks.

Regards,

Aik Eu


0 Kudos
Balkesh
Beginner
328 Views

Hello @aikeu ,

 

thanks for your response, Actually I already have taken the reference from some of the document which is mentioned above but i'm still at the question that how hps will get the descriptor which i've written so that msgDMA perform transaction from AVST to AVMM.

 

Suppose some packet is comming in the streaming mode and now i want to store them in the memory, as we know memory have different interface i.e. AVMM now in order to store data msgDMA should convert them in AVMM but msgDMA can not perform that transaction without the descriptor. Therefore i've used hps to provide the descriptor information to msgDMA for which i've written the .c and .h file but i'm not able get the steps how should i give it to the hps so that it provide to msgDMA.

 

regards

Balkesh

0 Kudos
aikeu
Employee
316 Views

Hi Balkesh,


I found this msgdma example using Cyclone V which may help for your reference:

https://blog.reds.ch/?p=835

https://gitlab.com/reds-public/msgdma_example/-/blob/master/md5/soft/drv/msgdma.c?ref_type=heads


Thanks.

Regards,

Aik Eu


0 Kudos
aikeu
Employee
239 Views

Hi Balkesh,


I will close the thread and transition it to community support if there is no further question.


Thanks.

Regards,

Aik Eu


0 Kudos
aikeu
Employee
207 Views

Hi Balkesh,


As we do not receive any response from you on the previous question/reply/answer that we have provided. Please login to ‘https://supporttickets.intel.com/s/?language=en_US’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.


Thanks.

Regards,

Aik Eu


0 Kudos
Reply