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Valued Contributor III
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Assmerbler: Can't use configuration device EPCQL256 with selected programming mode

Hi all, 

 

I am trying to recompile the PCIE Avalon-MM DMA reference design for Arria 10 (http://www.alterawiki.com/wiki/reference_design:_gen3x8_avmm_dma_-_arria_10). Since I modified a register in top.qsys file, it seems that I need to recompile the entire project to make the change effective. However, during the "Assembler" step of the compilation, I encountered an error as follows:  

 

Error (210027): Can't use configuration device EPCQL256 with selected programming mode 

I actually don't know what it means, let alone how to resolve it.  

There seem to be something vague in the error message. For example, what is a "selected programming mode"? Where can I check what the currently selected programming mode is? And how should I change it? 

 

Tried googling this error but only found this: http://quartushelp.altera.com/14.1/mergedprojects/msgs/msgs/epgmio_invalid_asm_mode_for_device.htm, which doesn't seem to be too useful. Does anyone has similar experiences? Would you mind give me some hints regarding this issue? 

 

Sorry for the newbie question. Any suggestion is much appreciated! 

 

(P.S. I am using Quartus Prime Standard Edition 17.0 out of box on a ubuntu 14.04 LTS.)
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Valued Contributor III
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In order to proceed in helping you, I need gather your info. 

 

First, you may confirm your programming mode as shown in picture 2, picture 3, and picture 4. If this fix the problem, just skip next step(s). Also, make sure you selected correct device in picture 4 device window. 

 

Second, which one are you converting your sof file into jic or pof or etc, please provide me the info. 

 

Third, if you still faced problem, share me your log while compile like shown in picture 1. You may attach the windows while compile to get the log. 

 

Share me your board info like board model/kit, memory type, JTAG/AS/etc header, for second and third solving to proceed. Programming mode is determined by the connector and flash memory you are using. 

 

Would suggest that: 

https://www.altera.com/products/boards_and_kits/all-development-kits.html (https://www.altera.com/products/boards_and_kits/all-development-kits.html

Download, install and compiled the h/w and s/w files for the kit model. Then, program them using the instruction in the pdf documentation. 

For custom board, paste full/all compile log here. 

 

Regarding error 210027, an alternative manual method to select device is open your .qsf file using notepad, fix the line e.g. set_global_assignment -name FAMILY "Arria 10 (GX/SX/GT)". Not recommended as pin assignment/etc settings might not be updated, it is recommended to go for picture 2, 3, 4 to select device and save it. 

 

Best Regards, 

Tzi Khang, Lim 

(This message was posted on behalf of Intel Corporation)
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Valued Contributor III
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Hi Tzi Khang, 

 

Thank you for the help! Below are my itemized responses to your questions: 

(1) My setting has been the same as you instructed in Pic 2 & 3. As for Pic 4, however, the picture seems to be largely compressed by the forum and the resolution is too low to see the content clearly. May I ask if you can post it somewhere else (e.g., on https://imgur.com/) and post the link here again? 

 

(2) I was not trying to convert the sof file to other programming file formats. Instead, I was just trying to re-compile the design. The reason for this recompilation was that, when I opened the arria 10 Avalon-MM DMA reference design (http://www.alterawiki.com/wiki/reference_design:_gen3x8_avmm_dma_-_arria_10) in Quartus 17, I was told by the tool that the Qsys IP (PCIe IP) used in that reference design needs to be upgraded; since the reference design was created with Quartus 16.0, I think this upgrade makes sense. However, after upgrading the IP in Qsys, I clicked the "compile" button again, and Quartus threw the Error 210027 message at the assembler step. 

 

(3) Please see the assembler error message below: 

Assembler report for top Mon Nov 13 10:50:13 2017 Quartus Prime Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition --------------------- ; Table of Contents ; --------------------- 1. Legal Notice 2. Assembler Summary 3. Assembler Settings 4. Assembler Encrypted IP Cores Summary 5. Assembler Generated Files 6. Assembler Device Options: top.sof 7. Assembler Messages ---------------- ; Legal Notice ; ---------------- Copyright (C) 2017 Intel Corporation. All rights reserved. Your use of Intel Corporation's design tools, logic functions and other software and tools, and its AMPP partner logic functions, and any output files from any of the foregoing (including device programming or simulation files), and any associated documentation or information are expressly subject to the terms and conditions of the Intel Program License Subscription Agreement, the Intel Quartus Prime License Agreement, the Intel MegaCore Function License Agreement, or other applicable license agreement, including, without limitation, that your use is for the sole purpose of programming logic devices manufactured by Intel and sold by Intel or its authorized distributors. Please refer to the applicable agreement for further details. +-----------------------------------------------------------+ ; Assembler Summary ; +-----------------------+-----------------------------------+ ; Assembler Status ; Failed - Mon Nov 13 10:50:13 2017 ; ; Revision Name ; top ; ; Top-level Entity Name ; top_hw ; ; Family ; Arria 10 ; ; Device ; 10AX115S2F45I1SG ; +-----------------------+-----------------------------------+ +----------------------------------+ ; Assembler Settings ; +--------+---------+---------------+ ; Option ; Setting ; Default Value ; +--------+---------+---------------+ +------------------------------------------------+ ; Assembler Encrypted IP Cores Summary ; +--------+------------------------+--------------+ ; Vendor ; IP Core Name ; License Type ; +--------+------------------------+--------------+ ; Altera ; Signal Tap (6AF7 BCE1) ; Licensed ; ; Altera ; Signal Tap (6AF7 BCEC) ; Licensed ; +--------+------------------------+--------------+ +---------------------------------------------------------------------------------------------------------------------+ ; Assembler Generated Files ; +---------------------------------------------------------------------------------------------------------------------+ ; File Name ; +---------------------------------------------------------------------------------------------------------------------+ ; /home/hsuch/Downloads/arria_10_pcie_ref_design/hip_a10gx_g3_x8_avmm_dma256_1602_PS_restored_se/output_files/top.sof ; +---------------------------------------------------------------------------------------------------------------------+ +-----------------------------------+ ; Assembler Device Options: top.sof ; +----------------+------------------+ ; Option ; Setting ; +----------------+------------------+ ; JTAG usercode ; 0xFFFFFFFF ; ; Checksum ; 0x30A76529 ; +----------------+------------------+ +--------------------+ ; Assembler Messages ; +--------------------+ Info: ******************************************************************* Info: Running Quartus Prime Assembler Info: Version 17.0.0 Build 595 04/25/2017 SJ Standard Edition Info: Processing started: Mon Nov 13 10:49:07 2017 Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off top -c top Info: Using INI file /home/hsuch/Downloads/arria_10_pcie_ref_design/hip_a10gx_g3_x8_avmm_dma256_1602_PS_restored_se/quartus.ini Warning (18236): Number of processors has not been specified which may cause overloading on shared machines. Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance. Error (210027): Can't use configuration device EPCQL256 with selected programming mode Error: Quartus Prime Assembler was unsuccessful. 1 error, 1 warning Error: Peak virtual memory: 8534 megabytes Error: Processing ended: Mon Nov 13 10:50:14 2017 Error: Elapsed time: 00:01:07 Error: Total CPU time (on all processors): 00:01:22  

 

(4) I am using the Arria 10 GX FPGA Dev Kit (https://www.altera.com/products/boards_and_kits/dev-kits/altera/kit-a10-gx-fpga.html) out of box. I am not sure how to identify some of the information you requested, such as memory type, JTAG/AS/etc header, etc. 

(5) Do I have to install anything other than the Quartus software and the Arria 10 device file to compile the reference design? 

 

Thank you very much for providing the help!
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Valued Contributor III
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I've already posted some response before this one but it seems that the forum moderator/manager has to approve it first before we can see it appear.  

 

So, before that shows up, I am also attaching the complete compile log in the attachment. 

 

Thank you!
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Valued Contributor III
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Hi, 

I notice the picture degrade so much until nothing can be seen. 

1. Since you are using original kit out of box, compile log is not needed. 

2. I put it in doc attachment so picture wont degrade, it is all about setting must be correct. 

3. qsf file is the one storing your setting, you may change from qsf file itself or open Quartus setting windows to change. For qsf file, you can also delete whole line instead of edit wording, Quartus is intelligent enough to replace correct setting. 

 

Best Regards, 

Tzi Khang, Lim 

(This message was posted on behalf of Intel Corporation)
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Valued Contributor III
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I met with this same error a while back, try opening the .qsf file with text editor and delete the line "set_global_assignment -name USE_CONFIGURATION_DEVICE ON"

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