Asynchronous signal synchronization

[Altera_Forum]

I have seen two circuit for synchronizing Asynchronous signal as the following shows: 

http://blogimg.chinaunix.net/blog/upfile2/080115160658.jpg  Any different between them?

[Altera_Forum]

Yes, the first is to synchronise a nReset signal, it has an output also without an active clock, the second to synchronize general signals, the problem I discussed in my reply to your previous posting.

[Altera_Forum]

Why don't use the second circuit to synchronise a nReset signal? 

Why don't use the first circuit to synchronise general signals?

[Altera_Forum]

The top circuit is design to go into reset asynchronously but come out of reset synchronously. The bottom circuit goes into and out of reset synchronously. The top circuit is important to use in cases were a reset stops the clock.

[Altera_Forum]

--- Quote Start ---  The top circuit is design to go into reset asynchronously but come out of reset synchronously. The bottom circuit goes into and out of reset synchronously. The top circuit is important to use in cases were a reset stops the clock.  --- Quote End ---    Got it... thanks... Welcome more info.

[Altera_Forum]

--- Quote Start ---  The top circuit is design to go into reset asynchronously but come out of reset synchronously. The bottom circuit goes into and out of reset synchronously. The top circuit is important to use in cases were a reset stops the clock.  --- Quote End ---    Can you explain more on the statement " The top circuit is important to use in cases were a reset stops the clock"? Don't get a clear picture here...

[Altera_Forum]

Hello, 

 you can answer the question yourself, if you ask: Could there be a reason to have a reset working without a clock present? If you see a reason, then you should use the first circuit, if not, use the "general" synchronisation circuit, as you like. One possible reason can be, that reset should cause all outputs to switch to a safe state.  Regards.  Frank