Avalon-MM Master Translator / Slave Translator gone in Quartus Prime Pro 19.4? (At least not visible)

[MKlee2]

I viewed an example design for ethernet/transceiver... in Quartus and noticed you handled the csr avalon-mm signal in a nice way using said ip (translator). I wanted to do something simmilar in my project, using 19.4 but I can't seem to find the ip. In my Standard (18.1) version it's visible under "Qsys interconnect", in pro it's gone, but because your example still works I guess I just can't see it? ("Intel FPGA Interconnect" doesn't shows it either, just a lot of stuff for -st connections)

So is there an alternative?

Edit: Just saw you changed the ip's properties to "INTERNAL" so it isn't meant to be used by users anymore?

Example name alt_em10g32_0_EXAMPLE_DESIGN

[Kenny_Tan]

This seems to be a bug to me. If standard had the interconnect, pro should have as well. Can you attached both of your design here in pro and std for me to investigate?

[MKlee2]

Well I don't have a complete design in pro or standard (std isn't possible => stratix), but I attached an example in std, which I want to build in pro.

To clarify stuff again:

Std is at version 18.1, here the IP is visible and NOT labled internal in its tcl

Pro is at 19.4, IP invisible because its property is set to internal

The example I got the idea from was generated using pro 19.4, but is targeting an older version, so I guess the internal change occured in 19.X.

(the IP also got updated to version 19.1 guess here it was changed)

IP-Name: Avalon-MM Master Translator Intel FPGA IP (+ slave)

IP-Name (tcl): altera_merlin_master_translator_hw.tcl (+ slave)

IP-Path: .\Quartus\ip\altera\merlin\altera_merlin_master_translator (+ slave)

New in 19.?: set_module_property INTERNAL true

Attached a simple qsys std 18.1 dummy showing what I want to do, I would also be fine with other ways/IPs to archiv this.

I just found it charming how you managed to handle the various control busses from 12 transceivers in one bus.

Also attached: MAC/xcvr/10G example generated by quartus pro

For now, because the ip is still there after all, I just copied it from an other .qsys into my design.

[Kenny_Tan]

I would be hard to make comparison without providing the standard edition of design. Have u look into the system -> show system with platform designer interconnect? It should have shown all the translator or extra interconnect over there.

[MKlee2]

Ok maybe we have some missunderstanding, the ip is still there and works and of course it shows up in "system -> show system with platform designer interconnect". It's just that I can't place it myself, because it's hidden from the "IP Catalog".

I'll attach some screenshots to make clear what I mean.

And like I said it is hidden because you changed it in a recent version to internal use only.

I can also include your ip .tcl files if you want.

[Kenny_Tan]

Thanks for clarifying providing the screenshot. this clear things out, I will get back to you if they were workaround on this

[Kenny_Tan]

Here is some feedback from the engineering:

Translator is meant to be used inside the interconnect with transform. Its parameterization depends on overall system configuration and can be correctly done by the transform. Hence the transform was removed from IP catalog. It still gets generated as part of interconnect.