Avalon Verification IP Suite questions

[Elit]

Hi.

I modified the avlmm_1x1_verilog_pro project from ug_avalon_verification.zip, adding Avalon-MM Monitor. 

According to Avalon Verification IP Suite User Guide, p.12:

The monitor components use the SystemVerilog Assertion (SVA) language and are
supported only by simulators that support SVA, including:
• ModelSim - Intel FPGA Edition
• Synopsys VCS
• Mentor Graphics® Questa.

However, when using Modelsim Intel FPGA Edition 19.4 Pro it issues messages like these:

** Warning: ip/avlm_avls_1x1/avlm_avls_1x1_mm_monitor_0/altera_avalon_mm_monitor_191/sim/altera_avalon_mm_monitor_assertion.sv(1097): (vlog-2186) SystemVerilog testbench feature
# (randomization, coverage or assertion) detected in the design.
# These features are only supported in Questasim.

Also I had to comment out altera_avalon_mm_monitor_coverage instantiation in altera_avalon_mm_monitor  module, to execute the run_simulation.tcl script without errors:

** Error: (vsim-1) Unable to checkout verification license - testbench generation feature (randomize, randcase, randsequence, covergroup) is only supported with QuestaSim.
Time: 0 ps Iteration: 0 Instance: .tb File: tb.sv
Error loading design
Error: Error loading design

Questions:

1. So, does Modelsim Intel FPGA Edition really support System Verilog Assertion?
2. Is it possible to get a verification license and if not, how to avoid errors without changing files?

Thanks,

Elit

[SyafieqS]

Hi Eliyahu,

Modelsim-Intel FPGA does not support for SVA. You can refer to KDB below. I will file a report for this as the document might be missing the updated information. You can request a Questasim license from Mentor since it is from Mentor. 

https://www.intel.com/content/altera-www/global/en_us/index/support/support-resources/knowledge-base/solutions/rd09072012_259.html

https://www.mentor.com/products/fv/questa/

Regards,

Syafieq

[Elit]

Thank you, Syafiq.

But I didn't get an answer to my second question : 

how to avoid Modelsim Intel FPGA edition errors without change altera_avalon_mm_monitor.sv file -

comment out instantiation of altera_avalon_mm_monitor_coverage module? 

Thanks,

Elit

[SyafieqS · Accepted solution]

Hi Eliyahu,

--- Is it possible to get a verification license and if not, how to avoid errors without changing files?---

Yes it is possible to get the license file and you can contact Mentor for that. Commenting out "altera_avalon_mm_monitor_coverage module" would result in following as you said

Error: (vsim-1) Unable to checkout verification license - testbench generation feature (randomize, randcase, randsequence, covergroup) is only supported with QuestaSim. 

Therefore, I guess the only way to proceed with this to use Questasim

Thanks,

Regards