Avalon specs changed on Altera transition (2020 document say this)

[RRomano001]

 Hello, I experienced a lot of trouble on MAX10 design.

 Translated to Xilinx to see how trouble can happen so an Avalon simulation was necessary.

 Acquiring document I seen spec changed from 2016 or 2017, this has time sync from when I started suffer strange issue.

 Doesn't explain why some VHDL term fail but explain some weird hang and failure.

 To what I felt Memory mapped master and slave no more generate by default datavalid in non burst mode.

Timing is solely driven by "waitrequest" not both.

 This required revise all my Ip core since 2014 .

  All core  (VHDL) work fine on Xilinx and when ported back to Altera Max10 too when not under Qsys design.

[KhaiChein_Y_Intel]

Hi,

Could you share the error message? What is the software edition (Pro/Standard) and version you are using?

Thanks

Best regards,

KhaiY

[RRomano001]

Hi Khai, no error was present, remember this was a revision to get my ip core run on Xilinx platform.

 All my core from Qsys template used both waitrequest and datavalid as from early 2014 specs.

 Reading latest document about avalon specs appeared as new release miss datavalid signal when non burst mode.

 No idea about old problem come from. May be Qsys avalon adapter or mixed language or a combination.

 Ported design, Qsys free perform same on xilinx and altera part too. What is not working on one side perform same way on both.

 New Avalon master memory arbitration IP core and memory controller was written to run core on xilinx spartan 6 as it was.

 After success running 100MHz design on Spartan an overclock was tested to 300MHz, no issue due it is pipelined. Spartan 6 has 450MHz limit and 280 on blockram.

 Ported back to Altera with some adaptation due slight difference between blockram and altsysram.

Compiled on quartus run fine when not under Qsys. A Module address PLL and ram so design can compile untouched on both platform, design change is shared to.

 Some Ip core written never got tested due to error discouraged me. 5 module remain to be debugged then full design can sell? Lock down also shortened market and industry.

From this I learned this was not my fault but some error from Qsys and or internal generated logic.

 No constraint nor design error.

NO idea why signal got mangled by.

 No idea why simple logic got weird result.

 Got idea about big loss of money and reputation.

 Design remain from now to retirement MUST be platform independent so no more  Qsys and probably no more Altera.

[sstrell]

It's hard to understand what the issue is here without code or error/info messages.  It sounds like you are maybe referring to the readdatavalid signal required for a pipelined transaction (there is no signal called just "datavalid")?  Is your design not working or not even compiling?  I think more clarification is needed.