Avalon st single clock fifo CSR address

[srinivasan]

Hi,
I am using Avalon st single clock fifo...In that I want to enable the almost empty and almost full signal..For that I need to configure CSR address and CSR write data....

For this...I don't know to how to give CSR address and data...

Can anyone help me on this..

[SyafieqS]

Hi Srinivasan,

You may need to refer to link below for details related to Avalon-ST Single-Clock and Dual-Clock FIFO Cores- Thresholds.

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_embedded_ip.pdf#page=33