Barrel shifter coding using mux

[Altera_Forum]

I need help building a barrel shifter that uses multiplexers and has three columns as stated in the attachment. Please help!

[Altera_Forum]

What help do you need? what problems are you having doing it yourself?

[Altera_Forum]

--- Quote Start ---  What help do you need? what problems are you having doing it yourself?  --- Quote End ---    Yes I am new to VHDL and don't quite understand all the commands I have one barrel shifter constructed but I don't know how to combine the other two barrel shifters with the signal command and I don't know exactly how I would write the code to get all barrels to shift. I know I probably need to select a signal that acts like a switch.

[Altera_Forum]

Thats sounds plausible - have a go and come back here when you're having problems with your code.

[Altera_Forum]

--- Quote Start ---  Thats sounds plausible - have a go and come back here when you're having problems with your code.  --- Quote End ---     library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.all;     entity barrel_shifter_8bit is  Port (  data: in std_logic_vector(7 downto 0);  data_out: out std_logic_vector(7 downto 0);  ctrl: in std_logic_vector(2 downto 0)  ); end barrel_shifter_8bit;   architecture Behavioral of barrel_shifter_8bit is   begin  with ctrl select  data_out<= data(0)& data(7 downto 1) when "001",  data(1 downto 0)& data(7 downto 2) when "010",  data(2 downto 0)& data(7 downto 3) when "011",  data(3 downto 0)& data(7 downto 4) when "100",  data(4 downto 0)& data(7 downto 5) when "101",  data(5 downto 0)& data(7 downto 6) when "110",  data(6 downto 0)& data(7) when "111",  data when others; end architecture Behavioral;  -----This is what I have so far I'm stuck on transfering the output to the next column of the barrel shifter.

[Altera_Forum]

library IEEE; 

use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.all;     entity barrel_shifter_8bit is  Port (  data: in std_logic_vector(7 downto 0);  data_out: out std_logic_vector(7 downto 0);  ctrl: in std_logic_vector(2 downto 0)  ); end barrel_shifter_8bit;   architecture Behavioral of barrel_shifter_8bit is   component barrel_shifter_8bit1 is  Port (  input: in std_logic_vector(15 downto 0);  data_out: out std_logic_vector(7 downto 0);  ctrl: in std_logic_vector(2 downto 0)  ); end component;   component barrel_shifter_8bit2 is  Port (  input: std_logic_vector(15 downto 0);  data_out: out std_logic_vector(7 downto 0);  ctrl: in std_logic_vector(2 downto 0)  ); end component;   component barrel_shifter_8bit3 is  Port (  input: in std_logic_vector(15 downto 0);  data_out: out std_logic_vector(7 downto 0);  ctrl: in std_logic_vector(2 downto 0)  ); end component; signal sig1, sig2: std_logic_vector; begin unit1: barrel_shifter_8bit1 port map (data7 =>input0, data6=>input1 and input2, data5=>input3 and input4,data4=>input5 and input6, data3=>input7 and input8, data2=>input9 and input10, data1=>input11 and input12, data0=>input13 and input14, input0 => 0); unit2: barrel_shifter_8bit2 port map(   unit3: barrel_shifter_8bit3 port map() end str_arch;  with ctrl select  data_out<= data(0)& data(7 downto 1) when "001",  data(1 downto 0)& data(7 downto 2) when "010",  data(2 downto 0)& data(7 downto 3) when "011",  data(3 downto 0)& data(7 downto 4) when "100",  data(4 downto 0)& data(7 downto 5) when "101",  data(5 downto 0)& data(7 downto 6) when "110",  data(6 downto 0)& data(7) when "111",  data when others; end architecture Behavioral;    ---- what it looks like now working on port mapping the three columns of barrel shifters. The last part is from some help I got earlier for the first column dont know how to use it yet.