Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
16556 Discussions

Below warning was reported for clock by Quartus Prime 18.0

XQSHEN
Novice
496 Views

Software: Quartus Prime 18.0

Device: 10M16DCU324I7G

 

Below warning is reported after run Fitter.

What's the problem here and what should I do?

 

Warning (332060): Node: emmc_driver:emmc_driver_0|clk_div[2] was determined to be a clock but was found without an associated clock assignment.

 

Verilog code: just use 50MHz to devide to generate 12.5MHz for eMMC write FIFO. It's customized component (I defined it as eMMC driver) used in NIOS system.

 

 always @(posedge clk) clk_div <= clk_div + 3'd1; // clk=50MHz

 assign ddrfifo_clk = clk_div[2]; //12.5MHz

0 Kudos
3 Replies
Kenny_Tan
Moderator
479 Views

You may need to write a sdc and create a clock for this. You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf

 

Thanks

0 Kudos
Kenny_Tan
Moderator
479 Views

Any update?

0 Kudos
XQSHEN
Novice
479 Views

You are right. you can close it.

0 Kudos
Reply