Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Below warning was reported for clock by Quartus Prime 18.0

XQSHEN
Novice
676 Views

Software: Quartus Prime 18.0

Device: 10M16DCU324I7G

 

Below warning is reported after run Fitter.

What's the problem here and what should I do?

 

Warning (332060): Node: emmc_driver:emmc_driver_0|clk_div[2] was determined to be a clock but was found without an associated clock assignment.

 

Verilog code: just use 50MHz to devide to generate 12.5MHz for eMMC write FIFO. It's customized component (I defined it as eMMC driver) used in NIOS system.

 

 always @(posedge clk) clk_div <= clk_div + 3'd1; // clk=50MHz

 assign ddrfifo_clk = clk_div[2]; //12.5MHz

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Kenny_Tan
Moderator
659 Views

You may need to write a sdc and create a clock for this. You may refer to https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/manual/mnl_timequest_cookbook.pdf

 

Thanks

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Kenny_Tan
Moderator
659 Views

Any update?

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XQSHEN
Novice
659 Views

You are right. you can close it.

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