Software: Quartus Prime 18.0
Below warning is reported after run Fitter.
What's the problem here and what should I do?
Warning (332060): Node: emmc_driver:emmc_driver_0|clk_div was determined to be a clock but was found without an associated clock assignment.
Verilog code: just use 50MHz to devide to generate 12.5MHz for eMMC write FIFO. It's customized component (I defined it as eMMC driver) used in NIOS system.
always @(posedge clk) clk_div <= clk_div + 3'd1; // clk=50MHz
assign ddrfifo_clk = clk_div; //12.5MHz