Best debugging tool for my situation?

[Altera_Forum]

Hello people! 

 I have created a small project for the DE0-Nano using the block editor and some custom FiniteStateMachine VHDL code to act as a ADC interface. I am using the ADS7953 of TexasInstruments which has an SPI interface but that doesnt really affect the question.  Basically now that -via simulation- my code seems to work just fine I need to test it realtime but using the onboard LEDS or an external LCD screen to test the real measurements is not a go.  So setting up the test configuration with the ADC and a real current source through it, which is the best debugging tool that I should use to see the values inside the FPGA using Quartus? By "values" I mean a collection of 16bit registers that I use to store the SPI decoded values from my state machine.  Any ideas folks?  Thanks!

[Altera_Forum]

It's called SignalTap II Logic Analyzer. You can find it under Tools menu in Quartus. You must set your system clock and signals to be monitored, compile the design and start debug procedure.

[Altera_Forum]

Thanks! 

 The monitored signals can be any signal inside the FPGA? Do I need a special block in my design to act as an intermediate?

[Altera_Forum]

As suggested previously, the use of Signal Tap will get you where you need to go. Make sure to use enough sample depth to see the input frequency signals that you want. If you need to, you can make the clock in Signal Tap really a clock enable that is corresponding to the sample rate. This is simple hardware handshaking type of "Start" pulse to the ADC module. You may need to run the output of the ADC into a small section of logic, such as a comparator or something, so that Quartus does not synthesize away the ADC module itself. I have tested ADC modules in this manner several times. For example, the ADS7945 I have done this way and is similar to the part you are using. One more simple trick is to use a PWM DAC that will take the output register value of the ADC and drive a FPGA with a PWM value. If you use a small RC filter on this pin you can recover your analog signal. If you do this, you get the double benefit of being able to see your signal and Quartus not synthesizing away the actual ADC module. Best, James

[Altera_Forum]

Yes, you can monitor all signals inside the FPGA. Quartus II creates everything else for you.

[Altera_Forum]

Hey thanks a lot! 

 I do not need to get the measurements this way, though, since I have already created the SPI interface for the ADC. Just for my information, I have a question here: Is there any ready made SPI interface block in the standard library? I couldn't find it and I have the inkling that this is due to the fact that SPI is no formal standard.  In my setup i use the classic external 50MHz crystal of DE0-Nano and inside I elevate the clock through a PLL block to 450MHz. I hope that Cyclone IV withstands that frequency. For the sampling part the SPI clocking is done at 18.75MHz.  End point is that I just want to see that my custom made SPI interface successfully communicates with the ADC chip and gets the 16bit values to the registers.

[Altera_Forum]

There is SPI block in QSYS, I think it is designed to be used with Nios II, but with some effort one can use it alone too. Perhaps it is easier to write SPI block by yourself in this case. 

 I am pretty sure, that you have huge timing problems in your design. Look here in the forum about TimeQuest timing analyzer, do the timing analysis, constrain the paths, learn maximal speed of your design and then perhaps you would need no SignalTap II anymore.