Bit error tester to test FPGA

[Altera_Forum]

the PRBS generates bits using 4 bit LFSR. i want to test for the bit error at the receiver using VHDL code. Using FIFO would be a good option to store the bits one by one? 

 And the same LFSR can be used at the receiver to compare it with the received bits right?

[Altera_Forum]

--- Quote Start ---  the PRBS generates bits using 4 bit LFSR. i want to test for the bit error at the receiver using VHDL code. Using FIFO would be a good option to store the bits one by one?  And the same LFSR can be used at the receiver to compare it with the received bits right?  --- Quote End ---    right. But you don't need fifo to store. Just generate tx prbs, send it as it generates. At receiver use an instant of same prbs with same seed but activate it when rx data arrives (after some delay).

[Altera_Forum]

i have attached the vhdl code for the reciever. I have generated the same pseudo random sequence as that of the txr, in the rxr also and compared each bit with the received data. If the value is different , count is incremented. 

 I am constantly getting the following error: 1. No feasible entries for infix operator "xor". 2. Type error resolving infix expression "xor" as type std.standard.boolean.   library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; use ieee.std_logic_arith.all; use ieee.std_logic_textio.all; -- entity ber is  port ( rxd_bit : in std_logic;  clk : in std_logic);    end ber;   architecture ar of ber is type data is array(0 to 63) of std_logic; signal d: data; signal c,m,t: integer:=0; signal count: integer:=0; signal q:bit_vector(3 downto 0):="0001"; signal k:bit_vector(3 downto 0);   begin  process(clk) is    begin  for c in 0 to 63 loop  if rising_edge(clk) then  d(c)<= rxd_bit;    end if;  end loop;    for i in 0 to 15 loop  q<=(q(2)xor q(3)) &q(0)&q(1)&q(2);  k<=q;     for t in 0 to 3 loop  if(k(t) xor d(t)) then ---------------------> error in this line  count<= count+1;  m<= m+1;  end if; end loop; end loop; end process; end ar;

[Altera_Forum]

-- entity ber is port ( rxd_bit : in std_logic; clk : in std_logic); end ber;  

 I suggest using some output flag. Moreover use numeric_std rather other libraries for type conversion   architecture ar of ber is type data is array(0 to 63) of std_logic; signal d: data; signal c,m,t: integer:=0; signal count: integer:=0; signal q:bit_vector(3 downto 0):="0001"; signal k:bit_vector(3 downto 0);   you don't need to declare c,t as they are loop indices m is doing nothing use std_logic and std_logic_vector. No need to mix with bit_vector.   begin process(clk) is begin for c in 0 to 63 loop if rising_edge(clk) then d(c)<= rxd_bit; end if; end loop;   this is not saving 64 input samples but just repeating one sample 64 times into 64 bits  for xor I will write if (a xor b) = '1' then

[Altera_Forum]

Thanks for the inputs. 

yes i realised that .

[Altera_Forum]

OK, you don't really need to save input bits. Instead put enable on your prbs(by the way that loop on prbs is not needed). you check when your input arrives and enable prbs first output with first input then prbs will run hand in hand with input bits per clock cycle.

[Altera_Forum]

I am kind of confused as to how to enable the output of prbs to be in sink with the incoming received bits to make the comparison to check for bit error.

[Altera_Forum]

--- Quote Start ---  I am kind of confused as to how to enable the output of prbs to be in sink with the incoming received bits to make the comparison to check for bit error.  --- Quote End ---    if you have real tx/rx system in action then you expect some delay for data to reach rx from tx. Thus the rx must generate a data valid signal to indicate validity of data. You wait for this valid to appear and use as enable for your prbs.

[Altera_Forum]

I am facing similar problem.  

 I am using an optical fiber to transmit the data. So there will be delay. Can you write the part of the code that will do the waiting for data and enabling checking?

[Altera_Forum]

--- Quote Start ---  I am facing similar problem.   I am using an optical fiber to transmit the data. So there will be delay. Can you write the part of the code that will do the waiting for data and enabling checking?  --- Quote End ---    You don't expect rx valid to appear from somewhere. It is you rx design front end that receives data, processes it and decides that it is now "locked" This may involve many complex modules if you are talking about say wireless (analogue stage) e.g. carrier tracking, clock recovery, demapping and so on depending on your design.  The Tx can send cyclical prbs, process data, modulate, filter, upsample etc then send to rx.  The Rx reverses all processes and when data processing is ready you generate data valid.  Since tx is sending data in a cyclic way then you can sync your rx prbs to beginning of any cycle once ready.

[Altera_Forum]

Thank you!!  

 I am stuck with an error in my hdl code. It is for bit error rate testing :  library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.numeric_std.all; entity ber is  port ( clk : in std_logic  );   end ber;   architecture ar of ber is   type data is array (0 to 11) of std_ulogic; signal d: data; -- give the input data bit by bit  signal q:std_logic_vector(0 to 3):="0001"; --signal rxd_bit:std_logic_vector(0 to 3):="1010"; -- shd be received from the txr signal k:std_logic_vector(0 to 3):="0000"; signal j,t: std_ulogic:='0';     begin    p1: process(j)  variable count : integer := -1;     begin      for j in 0 to 3 loop  p2: process(t) -----------> ERROR : illegal sequential statement  variable m: integer := 0;   begin  m:=m+1;   exit when m=5;  q<=(q(2)xor q(3)) &q(0)&q(1)&q(2);   k<=q;     for t in 0 to 3 loop  if (k(t) /= d(t+(4*(j-1)))) then   count := count+1;   end if;  end loop;   end process p2;     end loop ;  end process p2; end ar;  Can I use a process inside another process?