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Valued Contributor III
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Block Diagram File with Parameters - Generate VHDL File not possible (for Simulation)

Hello, 

please tell me if i got something wrong in my workflow: 

 

1. My Top-Level File is a BDF (Block Diagram File) 

2. I placed VHDL Blocks including Generics which are seen as parameters in the BDF. There i can set a parameter e.g: 

 

 

 

parameter 

value 

type 

 

 

COUNT_MAX 

1000 

Signed Integer 

 

 

SOMETHING_ELSE 

20.5 

Float 

 

 

 

I even can write a Variable instead of the number, e.g: 

 

 

 

parameter 

value 

type 

 

 

COUNT_MAX 

GLOBAL_PARAM_CNT_MAX 

Signed Integer 

 

 

SOMETHING_ELSE 

GLOBAL_PARAM_RANDOM 

Float 

 

 

 

3. The GLOBAL_PARAM_CNT_MAX can be set by the "Parameter Primitive" or e.g. in the Settings->Comiler Settings-> Default Parameters 

 

4. Everthing is fine, the design is synthesizable and the Parameters can be changed and set up by a Revision very easily! Perfect! 

 

Now my Problem. I want to simulate my design by the "build in" modelsim altera startet edition. So, as far as i understand and already did earlier, i have to generate a VHDL of the BDF and write a Test Bench for ist. Very easy in theory. Since there are Parameters inside the BDF, it is not possible to generate a VHDL by "File->Create/Update->Generate HDL File" as it shows up the error: 

 

Error (275082): Illegal values "GLOBAL_PARAM_CNT_MAX " for parameter "COUNT_MAX ". The type is "Signed Integer". 

Error (12153): Can't elaborate top-level user hierarchy 

Error: Quartus Prime Create VHDL File was unsuccessful. 2 errors, 0 warnings 

Error: Peak virtual memory: 521 megabytes 

Error: Processing ended: Tue Jun 27 18:16:10 2017 

Error: Elapsed time: 00:00:00 

Error: Total CPU time (on all processors): 00:00:01 

 

So, how can i use parameters (in any way?) on a very clear BDF File and somehow do a design simulation in Modelsim? -> I have LOTS of parameters. Just replacing the parameters by direct values for simulation/HDL file generation is no solution :-( Or is it simply a BUG on Quartus Prime Version 16.1? 

 

Thank you very much!
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Valued Contributor III
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Probably not a bug - just weaknesses in BDF. 

Easiest option is probably just write in VHDL in the first place.
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