Bug msgdma ? - connecting JESD204 to ddr memory via msgdma

[robertzab]

Hi,

I am building a project aimed at saving data from the JESD204 interface to DDR4 memory using the msgDMA module.

JESD204 is configured as - LMF - 882. So use 8 links. There are 256 bits of data in the output.

MSGDMA is configured as streaming - Memory mapped.

I wanted to make the system as follows. In parentheses I find the name of the configuration:

JESD204 (jesd.png) --> DCFIFO (dcfifo_1.png) --> MSGDMA (msgdma_1.png) --> DDR4

DCFIFO - symbol per beat: 32, Bits per symbol: 8.
msgdma - Data width: 256

Unfortunately, the error on the DCFIFO side:
"The source has 256 bits per symbol, while the sink has 8."

By changing the configuration:
DCFIFO - symbol per beat: 1, Bits per symbol: 256
msgdma - Data width: 256

Error on MSGDMA side:
"The source has 256 bits per symbol, while the sink has 8."

I found in the UG-01085 documentation dated 2020.09.21 (doc_1.png) that it should support this type of format.

Is this an error of the msgda module? am I just doing something wrong?

I use the Arria 10 GX Development Kit with PN 10APCIe0003927.
Quartus version 19.4.0. I also checked this module in version 20.2.
Operating System: Windows 10pro

The attachment also includes a simple program simulating the above case.

[AnilErinch_A_Intel]

Hi ,

Please let us know whether the work around has been found.

You can always make use the working reference designs like those given in below link as a starting point for comparing the configurations.

https://community.intel.com/t5/FPGA-Wiki/MSGDMA-design-example/ta-p/735335

Thanks and Regards

Anil