We have been using Quartus as a teaching tool for many years, but unfortunately have been "stuck" on version 13.0sp1 due to the FPGA board (DE2) we had for students (13.0sp1 is the latest version that supports the FPGA on that board). One lab sequence designs, simulates, and exercises a subset of the MIPS architecture as presented in the Hennesey/Patterson text book. The ALU is built hierarchically, starting with a 1-bit ALU to generate a 32-bit ALU. (Remember, this is a teaching exercise!). The VHDL code generated by Quartus II for the 1-bit ALU is incorrect (would fail compilation in Modelsim) due to the output of the LPM_ADDSUB with a width parameter of 1 bit not be handled correctly. For years, we instructed the students how to edit the generated VHDL to "fix" the error since we figured this was probably reported and fixed in later Quartus releases. This year we purchased newer FPGA boards (DE10) and I'm in the process of updating the labs to use Quartus Prime (v18.1.1) and have found that it still produces this error.
The edit to the VHDL code is simple, but the tool should not produce bad code. The attached files show the "generated" VHDL and the corrected VHDL. The error occurs on line 80 and is due to the signal SYNTHESIZED_WIRE_8 being declared (properly) as a STD_LOGIC, but being referenced on line 80 as a single bit slice (via the "(0)" indication).
The LPM_ADDSUB module was selected as "Add only" with a width of 1 bit, and has both a carry-in and carry-out (eg. 1-bit full adder).
I looked all over the web site to try to figure out where to report a Quartus problem... I take it that the forums are the appropriate place...