When the data type is declared in the generic package, the synthesis tool removes the signal completely when array slice is used on the right side of the assignment. I have condensed it to the following minimal example. The output signal o_bug in this example does not have any driver:
package parallel_pixel_type_pkg is new work.chr3_pkg_generic
generic map(PARALLEL_INPUT_CHANNELS => 1);
library ieee;
use ieee.std_logic_1164.all;
use work.parallel_pixel_type_pkg.all;
entity bug is
port(
i : in std_logic_vector(17 downto 0);
o_bug : out std_logic_vector(16 downto 0);
o_ok : out std_logic_vector(17 downto 0)
);
end entity;
architecture rtl of bug is
signal sp : test_type_t;
begin
sp.pixel_data(0) <= i;
o_bug <= sp.pixel_data(0)(16 downto 0); -- BUG: o_bug is not connected to i
o_ok <= sp.pixel_data(0); -- OK
end rtl;
Generic package looks like this:
--
library ieee;
use ieee.std_logic_1164.all;
package chr3_pkg_generic is
generic(PARALLEL_INPUT_CHANNELS : integer);
type spectrum_arr_t is array (integer range <>) of std_logic_vector(17 downto 0);
type test_type_t is record
pixel_data : spectrum_arr_t(PARALLEL_INPUT_CHANNELS - 1 downto 0);
end record;
end package chr3_pkg_generic;
--
I am using Quartus Prime Pro 19.3 and 21.3 on Windows 10. I am also attaching the project archive with the example.
Link Copied
Hi Ean,
the link to the stack overflow page does not apply here, it is completely different issue.
I have simplified my example further, so that two ports do not mislead anybody. Now there is only one signal at the output, and it is still not connected. I hope you can see the issue this time.
library ieee;
use ieee.std_logic_1164.all;
use work.parallel_pixel_type_pkg.all;
entity bug is
port(
i : in std_logic_vector(17 downto 0);
o_bug : out std_logic_vector(16 downto 0)
);
end entity;
architecture rtl of bug is
signal sp : test_type_t;
begin
sp.pixel_data(0) <= i;
o_bug <= sp.pixel_data(0)(16 downto 0);
end rtl;
Best regards,
Ivan
Hi Ean,
I am feeding some data into the i port of the design and monitoring the o_bug port. As expected, the o_bug port is equal to the i port.
Here is the testbench:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity bug_tb is
end bug_tb;
architecture test of bug_tb is
signal i: std_logic_vector(17 downto 0);
signal o_bug: std_logic_vector(16 downto 0);
begin
stimuli : process
begin
for j in 0 to 10 loop
i <= std_logic_vector(to_unsigned(j, 18));
wait for 1 ns;
end loop;
wait;
end process;
uut : entity work.bug port map(i => i, o_bug => o_bug);
end;Here is the result of the simulation.
As you can see, it works in simulation.
Best regards,
Ivan
P.S. It has been almost two weeks that i am trying to prove you that such simple construct as A<=B does not work in this case. I have provided an VHDL example, the proof in the RTL view, now we are down to simulating the basic VHDL A<=B construct. This is really a very basic VHDL. You have multiple times sent me completely false and misleading information, which leads me to believe that you do not have experience with that language. Is there anybody in support with VHDL knowledge who might have a look at it? Because realizing that the problem here is not due to "coding issues"(what does it even mean anyway?) should not take more then 10 min.
