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Building Quartus16.1 files on Quartus 16.0

Altera_Forum
Honored Contributor II
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Hi, 

 

So, I m working on top of a third party HDL framework, which is written specifically to be build on Quartus 16.1. It uses some of quartus IPs, (AlteraNative PHY just to name one, generated with Quartus 16.1). The build script organizes all these IPs and other design files, to make necessary quartus files(including qsf file and qpf files) and builds the same.  

 

So my question specifically is,  

 

1) Does building a project with QIPs generated and constrained for Quartus 16.1, cause timing closure to be difficult, building with 16.0?. 

 

The reason for the question, is lack of license support for 16.1, and hence I m evaluating the need for license upgrade, and to conclude that the difference in the quartus versions could be a reason for the timing violation(The same design had easy timing closure with previous version of framework which was constrained for a previous version of Quartus). 

 

Thanks in advance 

Jeebu
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Altera_Forum
Honored Contributor II
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Quartus changes between versions, and so the builds will not be identical for the same seeds. 

Also, if you havent got the source code generated, and are relying on built in libraries, IP blocks can be different between versions. 

 

So it is possible that it will not build at all between versions.  

But if it does build, you wont get the same results between tool versions for the above reasons, and there may be compiler changes. 

 

You could try changing the seed to get a different result, but it will never match a different tool version.
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Altera_Forum
Honored Contributor II
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Thanks Tricky for the quick response,  

 

I had tried with a range of SEED values, and its not helping much. Had tried with an evaluation version of 16.1 too. For the couple of trials done with it, the timing closure is not consistent across the SEED sweep done. 

 

 

Regards 

Jeebu
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Altera_Forum
Honored Contributor II
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That is to be expected - changing the seed affects the build, but also note that changing the source code in any way, or changing the project settings, also changes the build, so a good seed will not be good for all builds and versions.

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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

Hi, 

 

So, I m working on top of a third party HDL framework, which is written specifically to be build on Quartus 16.1. It uses some of quartus IPs, (AlteraNative PHY just to name one, generated with Quartus 16.1). The build script organizes all these IPs and other design files, to make necessary quartus files(including qsf file and qpf files) and builds the same.  

 

So my question specifically is,  

 

1) Does building a project with QIPs generated and constrained for Quartus 16.1, cause timing closure to be difficult, building with 16.0?. 

 

The reason for the question, is lack of license support for 16.1, and hence I m evaluating the need for license upgrade, and to conclude that the difference in the quartus versions could be a reason for the timing violation(The same design had easy timing closure with previous version of framework which was constrained for a previous version of Quartus). 

 

Thanks in advance 

Jeebu 

--- Quote End ---  

 

 

Generally it is recommended to compile/use the IP generated in a specific version ie 16.1 in same Quartus version 16.1 or newer. If you use the IP with older Quartus version, it might not be compatible. 

 

Best Regards, 

bfkstimchan 

(This message was posted on behalf of Intel Corporation)
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

That is to be expected - changing the seed affects the build, but also note that changing the source code in any way, or changing the project settings, also changes the build, so a good seed will not be good for all builds and versions. 

--- Quote End ---  

 

 

Tricky is right. with different compilation configuration, the placement, routing and internal resource utilization would change. This is why you would see different timing results with these different builds. 

 

 

Best Regards, 

bfkstimchan 

(This message was posted on behalf of Intel Corporation)
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