C10GX serdes TX ext pll valid clk source?

[DeepSubMicron]

For an HDMI output on an Cyclone 10 GX we need a serdes transmitter IP with reconfigurable clock.

So an LVDS SERDES with external PLL for reconfiguration.

The reference clock for most PLL should be an 50MHz input clock pin. As well for the HDMI SERDES PLL.

What are the requirements for the reference clock and how to fix this error:

Error(18694): The reference clock on PLL "pll_hdmi|iopll_0|altera_iopll_i|c10gx_pll|iopll_inst", which feeds an Altera LVDS SERDES IP instance, is not driven by a dedicated reference clock pin from the same bank. Use a dedicated reference clock pin to guarantee meeting the LVDS SERDES IP max data rate specification.

Btw. the 50MHz clock pin should also be the reference clock for the DDR3 memory controller.

[EngWei_O_Intel]

Hi Jens Kuenzer

Please refer to similar issue below:

https://community.intel.com/t5/Intel-Quartus-Prime-Software/How-to-workaround-the-ERROR-ID-18694/td-p/709949

We shall always use a dedicated reference clock pin per PLL that drives an Altera LVDS SERDES IP instance.

Thanks.

Eng Wei

[DeepSubMicron]

Does dedicated reference clock mean I can't multidrop that pin to other pll, like ddr3 memory controller?

If the pin is driving the SERDES PLL directly then the jitter requirements for SERDES are met. At the same time driving another pll is impossible?

[DeepSubMicron]

I tried to connect the ref clock input pin to other plls as well. Then an error suggest to promote clocks to global clock for the other plls. So I used a clock control instance with global clock output.

The pll of the ddr3 memory controller does not like that because it expects a clock at PLL_CASCADE_IN which fitter tells me is incompatible to the global clock buffer output.

So it really looks like I need another clock pin.

[DeepSubMicron]

Well this more and more becomes a development blog.

After adding a dedicated pin for the PLL at the SERDES, next I tried to chain a 3rd pll to the ddr3 pll clock output.

I have tried that because it seems to me that ddr3 memory controller pll can not share ref clock input as well.

This causes an error message that IOPLL cascade chain of 3 or more IOPLLs was found:

- the ddr3 memory controller pll

- the 3rd pll

- the PLL at the SERDES (yes that with a dedicated refclock input)

Now, I am a little bit confused.

[DeepSubMicron · Accepted solution]

Another attempt:

Dedicated refclock input for SERDES PLL

Other refclock input promoted to global clock with clock control instance.

This global clock connected to all other PLLs.

That seems to work (so far).

[EngWei_O_Intel]

Hi Jens Kuenzer

Yes. Because SERDES IP data rate performance is sensitive to jitter, there is this restriction to have dedicated ref clock driving the PLL that feeds the SERDES IP.

Thanks.

Eng Wei

[DeepSubMicron]

Thanks for your answer. It does not explain how adding another sink is affecting the jitter of a clock.

I mean in an FPGA it does not even increase the cap load of the driving transistors. But I am no PLL designer.

I still think the problem may be just constraining the pin placement  to the iopll placement is not very intuitive. Since I failed doing so another clock pin is my workaround.