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CANT LOAD DESIGN

ASWATHYV_V_11
Beginner
144 Views

 

HAI,

CAN ANYBODY RESOLVE THIS ERROR 

# FATAL ERROR while loading design
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./INT_TOP_run_msim_rtl_vhdl.do PAUSED at line 22

AND THE INT_TOP_run_msim_rtl_vhdl.do  FILE IS COPIED HERE.

transcript on
if {[file exists rtl_work]} {
vdel -lib rtl_work -all
}
vlib rtl_work
vmap work rtl_work

vlog -vlog01compat -work work +incdir+C:/Users/user/Desktop/FPGA\ TESTING_INTEG\ NODE/JAN12\ FILES\ FROM\ KP/INT_TOP_13JAN2021/db {C:/Users/user/Desktop/FPGA TESTING_INTEG NODE/JAN12 FILES FROM KP/INT_TOP_13JAN2021/db/plll_altpll.v}
vcom -93 -work work {C:/Users/user/Desktop/FPGA TESTING_INTEG NODE/JAN12 FILES FROM KP/INT_TOP_13JAN2021/INT_TOP.vhd}
vcom -93 -work work {C:/Users/user/Desktop/FPGA TESTING_INTEG NODE/JAN12 FILES FROM KP/INT_TOP_13JAN2021/adc_interface_logic.vhd}
vcom -93 -work work {C:/Users/user/Desktop/FPGA TESTING_INTEG NODE/JAN12 FILES FROM KP/INT_TOP_13JAN2021/fifo.vhd}
vcom -93 -work work {C:/Users/user/Desktop/FPGA TESTING_INTEG NODE/JAN12 FILES FROM KP/INT_TOP_13JAN2021/digipot_config.vhd}
vcom -93 -work work {C:/Users/user/Desktop/FPGA TESTING_INTEG NODE/JAN12 FILES FROM KP/INT_TOP_13JAN2021/spi_slave.vhd}
vcom -93 -work work {C:/Users/user/Desktop/FPGA TESTING_INTEG NODE/JAN12 FILES FROM KP/INT_TOP_13JAN2021/plll.vhd}
vcom -93 -work work {C:/Users/user/Desktop/FPGA TESTING_INTEG NODE/JAN12 FILES FROM KP/INT_TOP_13JAN2021/psram_buffer.vhd}
vcom -93 -work work {C:/Users/user/Desktop/FPGA TESTING_INTEG NODE/JAN12 FILES FROM KP/INT_TOP_13JAN2021/psram.vhd}
vcom -93 -work work {C:/Users/user/Desktop/FPGA TESTING_INTEG NODE/JAN12 FILES FROM KP/INT_TOP_13JAN2021/dpram.vhd}
vcom -93 -work work {C:/Users/user/Desktop/FPGA TESTING_INTEG NODE/JAN12 FILES FROM KP/INT_TOP_13JAN2021/control_logic.vhd}

vcom -93 -work work {C:/Users/user/Desktop/FPGA TESTING_INTEG NODE/JAN12 FILES FROM KP/INT_TOP_13JAN2021/simulation/modelsim/INT_TOP_TB.vhd}

vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L fiftyfivenm -L rtl_work -L work -voptargs="+acc" INT_TOP_TB

add wave *
view structure
view signals
run -all

 

 

PLEASE HELP ME

0 Kudos
3 Replies
KennyT_Intel
Moderator
133 Views

May I know you are using Quartus Pro or Quartus std? If you use Quartus std, we do have a native link to help setting up it.


KennyT_Intel
Moderator
116 Views

Any update?


KennyT_Intel
Moderator
107 Views

We do not receive any response from you to the previous question. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions. 


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