CDC-50001 - 1-Bit Asynchronous Transfer Not Synchronized

[OrF]

the Quartus STA reports "CDC-50001 - 1-Bit Asynchronous Transfer Not Synchronized" 

sync-fifo in my design . 

at this document "AN 919: Improving Quality of Results with Design Assistant" :https://www.intel.com/content/www/us/en/docs/programmable/683369/current/clock-domain-crossing-and-reset-domain.html

the example shows same design  as I have , and it suggests to add another sample using clkb.

" the output of the blue register should feed another blue register to better protect against metastability."

but I do have 2 FF of sampling at the output - so bottom line I don't understand why my design fails at "Design Assistant (Signoff) Results" 

the precise question why the STA does not "see" the sync2_in register ? 

[sstrell]

Quartus may not be recognizing these registers as a synchronization chain.

What are your synch chain length settings (Compiler Settings -> Advanced Synthesis) and synchronizer identification settings (Timing Analyzer -> Metastability Analysis tab)?

[OrF]

I think it is 3 ? / is it the right option ?  and auto ? 

[sstrell]

Since it's set to 3 and you only have 2 registers in the destination clock domain, it's not getting recognized as a synch chain.  Add an extra register or reduce the chain length, though I'd recommend adding a register because it is much more common to have 2 registers in a row throughout your design so there would be a better chance of chains getting mis-identified.

[OrF]

Hi , 

I understand your solution - Thanks!  , but your last sentence is not clear "though I'd recommend adding a register because it is much more common to have 2 registers in a row throughout your design so there would be a better chance of chains getting mis-identified."

I DO have 2 registers in a row ... ( and yes all my design has 2 registers ) so I assume the recommendation should be reduce the "chain length settings" to 2 ?

Or. 

[sstrell]

No, I'm saying to make all your synch chains at least 3 instead of reducing the chain length to 2 so that only chains of 3 get recognized as synch chains.  If you reduce the setting to 2, there most likely be many series of 2 registers mis-identified as synch chains.

[OrF]

Hi 

Since I can not add another FF to  sample for the synchronizers ( inorder to increase the chain to 3) - I have change the setting from 3 to 2 with the next tcl command : 

"set_global_assignment -name SYNCHRONIZATION_REGISTER_CHAIN_LENGTH 2"

I see that Quartus capture this "setting" , but on the other hand I still get the same warning: " CDC-50001 - 1-Bit Asynchronous Transfer Not Synchronized "

any other reason for this warning ?  any option to for further debug  ?

[OrF]

any update about the issue ?