CRC error check in verilog

[m_kumar]

Hi 

can anyone help me how to implement an verilog code to check data integrity using CRC for polynomial calculation x11+x8+x7+x6+x4+x3+x1+1. 

i want to check data integrity at receiver side.

Thanks

regards

[ak6dn · Accepted solution]

Did you use the solution referenced in your previous post:

https://community.intel.com/t5/Intel-Quartus-Prime-Software/Help-needed-for-implementing-CRC-polynomials-in-verilog/m-p/1206976#M66104

Don't start a new post unless you really need to change the subject dramatically.

[ak6dn]

FYI just for fun I followed the instructions in the previous post for a CRC generator with a data width of 1, polynomial width of 12, with your requested polynomial, and it generated the following results:

 

[m_kumar]

sir is that logic work for 300Mhz clock source. 

thanks in advance

[ak6dn]

Well, that depends on a lot of things that have not been specified.

Device family, speed grade, layout.

So no way to say at this point.

The implementation is register based with probably just one level, or two at most, in the feedback logic.

So if 300MHz is a valid internal clock for a device, I would say a definite maybe.