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Altera_Forum
Honored Contributor I
1,240 Views

Call to set_clock_groups fails for Stratix 10 Build

When my SDC file is read while compiling for a Stratix 10 device, the set_clock_groups command is failing. The failure occurs because at the point in time that the SDC file is read, the tool does not know about derived clocks. My SDC file has the derive_pll_clocks included, but I get a statement "The derive_pll_clocks command is not supported in this family". So apparently I should not have to call this command. But the clocks that are referenced in my set_clock_groups command are not valid at the time the SDC file is read. However, they are valid later. For instance, if I go into TimeQuest I get the same failure initially with the set_clock_groups. If I run report_clocks the clock names that I used are valid. If I re-read the SDC file within TimeQuest the set_clock_groups command does not fail. So it appears that set_clock_groups has to occur after some later step in the SDC read process.

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7 Replies
Altera_Forum
Honored Contributor I
144 Views

 

--- Quote Start ---  

When my SDC file is read while compiling for a Stratix 10 device, the set_clock_groups command is failing. The failure occurs because at the point in time that the SDC file is read, the tool does not know about derived clocks. My SDC file has the derive_pll_clocks included, but I get a statement "The derive_pll_clocks command is not supported in this family". So apparently I should not have to call this command. But the clocks that are referenced in my set_clock_groups command are not valid at the time the SDC file is read. However, they are valid later. For instance, if I go into TimeQuest I get the same failure initially with the set_clock_groups. If I run report_clocks the clock names that I used are valid. If I re-read the SDC file within TimeQuest the set_clock_groups command does not fail. So it appears that set_clock_groups has to occur after some later step in the SDC read process. 

--- Quote End ---  

 

 

what stops you from directly setting clk group to the pll outputs (without using derive pll clocks). You can find the path name from node finder in timequest.
Altera_Forum
Honored Contributor I
144 Views

S10 clocks are constrained with the IP, so when you create a PLL or transceiver IP, it usually has an accompanying .sdc with it that constrains the clocks. You just want to make sure your .sdc is read in after this. If you go to Assignments -> Settings -> TimeQuest, push your .sdc to the bottom(or do it in Assignments -> Settings -> Files). After doing this, close TQ and re-open it(so it sees the changes) and see if that fixes it, before running a full compile.

Altera_Forum
Honored Contributor I
144 Views

 

--- Quote Start ---  

what stops you from directly setting clk group to the pll outputs (without using derive pll clocks). You can find the path name from node finder in timequest. 

--- Quote End ---  

 

 

Nothing. But I would prefer to use the derived names. But If all else fails, that is what I'll do.
Altera_Forum
Honored Contributor I
144 Views

As I mentioned the IP should be constraining the clocks and I recommend getting that to work rather than trying to do it on your own.

Altera_Forum
Honored Contributor I
144 Views

 

--- Quote Start ---  

As I mentioned the IP should be constraining the clocks and I recommend getting that to work rather than trying to do it on your own. 

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I was responding to the other post. I had to re-run because I regenerated one of my IP. I re-arranged the files, so I'm trying what you suggested. I should know shortly if changing the order helped with this issue. 

 

Thanks,
Altera_Forum
Honored Contributor I
144 Views

Different behavior when re-arranging the files. Two of my clock inputs (reference clocks coming into the FPGA) that I assigned in my SDC file are already assigned by the time I get to reading it. One was only used as the reference for an IOPLL and the other was the reference clock for a full-duplex LVDS block with soft CDR. Minor problem. I'll have to get back to TimeQuest to see what name these clocks are given in order to fix the set_clock_groups command. 

 

Thanks,
Altera_Forum
Honored Contributor I
144 Views

Resolved. Had to place one SDC file prior to the IP files to create_clocks on inputs. Then after all IP files i placed another SDC file that contained the set_clock_groups. 

 

Thanks,
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