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Hi sir/madam.
I'm designing an camera link logic to transmit rgb data to through camera link. I stuck with how to generate clock signals for both transmitter side and receiver side.
I studied one manual it was saying need to generate two clocks.
- base pixel clock.
- lvds bit clock ( i,e base pixel clock *7 /2 )
can i get any design references for to solve this problem
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Hi Kumar
Are you trying to create a LVDS SERDES function in FPGA or clock generation in FPGA?
Thanks.
Eng Wei
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Yes sir i'am using serializer in transmitter side and deserializer in receiver side.
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Hi Kumar
You can generate example design through IP Catalog following spec here:
Or you can search for relevant functional design example here:
https://fpgacloud.intel.com/devstore/platform/?search=LVDS
Thanks.
Eng Wei
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Hi Kumar
Since there is no update on this, we will transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.
Eng Wei
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