Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Can Avalon-MM Slave BFM Intel FPGA IP be used to implement a memory block?

gyuunyuu
New Contributor II
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In a memory block, reading the same address, shall give the same data value. Can this be implemented using the Avalon-MM Slave BFM Intel FPGA IP for verification purpose?

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gyuunyuu
New Contributor II
354 Views

The "Avalon Verification IP Suite: User Guide" mentions a memory_mode on page 47:

"Response Generator and Data Cache— In memory_mode the Slave BFM models a single port RAM. A write operation stores the data in an associative array and generates no response. A read operation fetches data from the array and drives it on the response side of the Avalon interface. This mode simplifies loopback testing. "

However, there is absolutely nothing with this name anywhere outside this document. I have done a search of the .sv file of the BFM. I have not found anything there. Is this some sort of mistake?

gyuunyuu
New Contributor II
315 Views

There is also this function called set_response_timeout which has been left inside the altera_avalon_mm_slave_bfm.sv but does absolutely nothing. Why is this so?

EricMunYew_C_Intel
Moderator
280 Views

The Avalon-MM Slave BFM is a bridge and cannot be used to implement memory block.


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