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Can not reply the topic "Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP"

ScottHu2021
Beginner
383 Views

Hi ,

 

I can not reply the topic "Instantiation of DDR3 SDRAM Controller with UniPHY intel FPGA IP - Intel Communities" any more.  Anybody can help me?

 

Thanks,

 

Scott

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9 Replies
AdzimZM_Intel
Employee
372 Views

Hi Scott,


The ticket that you have opened before has been closed due to inactive for a long period.


You can post your comment here.


Regards,

Adzim


ScottHu2021
Beginner
340 Views

Hi Adzim,

Currently, we have changed the hardware a little bit, that it,  add a 50M oscillator and assign its' output to one pin of DQ I/O bank as our discussed before.  Unfortunately,  the DDR3 still can not work with 300M frequency.  

The timing report of DDR controller is as following:

Initializing DDR database for CORE ddrc_p0
Finding port-to-pin mapping for CORE: ddrc_p0 INSTANCE: ddrc_u|ddrc_inst
Report Timing: Found 10 setup paths (0 violated). Worst case slack is 1.461
Report Timing: Found 10 hold paths (0 violated). Worst case slack is 0.303
Report Timing: Found 10 recovery paths (0 violated). Worst case slack is 11.060
Report Timing: Found 10 removal paths (0 violated). Worst case slack is 0.834
Core: ddrc_p0 - Instance: ddrc_u|ddrc_inst
setup hold
Address Command (Slow 1100mV 85C Model) | 0.975 0.968
Bus Turnaround Time (Slow 1100mV 85C Model) | 5.512 --
Core (Slow 1100mV 85C Model) | 1.461 0.303
Core Recovery/Removal (Slow 1100mV 85C Model) | 11.06 0.834
DQS vs CK (Slow 1100mV 85C Model) | 0.45 0.562
Postamble (Slow 1100mV 85C Model) | 0.817 0.817
Read Capture (Slow 1100mV 85C Model) | 0.315 0.268
Write (Slow 1100mV 85C Model) | 0.366 0.366

we also monitored the signal "local_cal_success" exported from the controller interface  together with the "local_init_done" , which are all  high after power-on.  So, the calibration and initialization process should succeeded.

BTW, in the "report top failing paths", there are some setup slack violations of NIOS address and data bus ( in our design, there is a NIOS implemented ), I am not sure if these timing violations will affect the DDR operation.

Regards,

Scott

ScottHu2021
Beginner
336 Views

Hi Adzim,

FYI:

The NIOS timing violation are as follows:

Slack                               from note                                                                                                             To Node

-6.263         NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|d_address_tag_field[12]         NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|A_dc_wb_rd_addr_offset[0]
-6.263         NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|d_address_tag_field[12]         NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|A_dc_wb_rd_addr_offset[0]~DUPLICATE
-6.262         NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|d_address_tag_field[12]         NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|A_dc_wb_rd_addr_offset[1]
-6.183         NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|d_address_tag_field[12]        NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|A_dc_wb_rd_addr_offset[0]
-6.183        NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|d_address_tag_field[12]         NIOS:nios_u|NIOS_nios:nios|NIOS_nios_cpu:cpu|A_dc_wb_rd_addr_offset[0]~DUPLICATE

...

 

please refer to the attached file for detailed information.

However, even with these timing violation, all functions implemented with NIOS can work well. 

 

Regards,

 

Scott

AdzimZM_Intel
Employee
317 Views

Hi Scott,


Thank you for the updates.


I'm not clear about the DDR3 is not working with the 300M frequency.

The timing report looks okay and the memory is passing the calibration like you said.


But maybe for now you can test the design with only the EMIF IP to see if the memory interface can work or not.


Regards,

Adzim


ScottHu2021
Beginner
300 Views

Hi Adzim,

 

I create a small project dedicated to test the DDR3.  Please refer to the attached project archive. 

In this project,  50M clock is used as the pll_ref_clock of ddr controller , and a derived 100M clock will drive the logic which reads/ writes DDR.

After programming the FPGA, I can not monitor the assert of the signal "local_cal_success".  May you give me some hints about this problem?

 

Thanks!

 

Scott

ScottHu2021
Beginner
286 Views

Hi Adzim,

 

The DDR3 test project was updated,

If we set the PLL reference clock 's frequency to 50M and connect the external 50M clock to the pll_ref_clk, the test failed. 

if we set the PLL reference clock's frequency to 100M and connect the external 50M clock to the pll_ref_clk, the test passed ( the write data equals to the data read back).  

Please refer to the attached project archive.

 

Thanks,

 

Scott.

AdzimZM_Intel
Employee
286 Views

Hi Scott,


Happy New Year!


You can use Signal Tap tool or EMIF Debug Toolkit tool to analyze the signal.

I think with the EMIF Debug Toolkit, you can see the calibration process and get the calibration report as well.


Can you check the clock frequency on the board as well?


Also is that possible for you to test the design with another board or memory device?


Thanks.

Regards,

Adzim




ScottHu2021
Beginner
270 Views

Hi Adzim,

 

With the configuration "PLL reference clock's frequency: 100M and  the 50M clock connection to the pll_ref_clk", the device can connect to the External Memory Interface Toolkit and finish the calibration procedure. But with the configuration "PLL reference clock's frequency: 50M",  the device can not connected to the toolkit.

 

Would you like to compile the project attached in this post?  It is a very simple project to initialize a DDR3 controller and performs data write and read and then compare the data readback with the last write value. The PLL reference clock frequency is configured as 50M.

Even with this simple implementation, there are still some timing violations with the DDR3 controller. With my poor experience, I do not know how to fix these timing issues. Would you like to give some hints?

 

Thanks and happy new year too!

 

Scott

 

 

 

 

AdzimZM_Intel
Employee
249 Views

Hi Scott,


I can see the timing issues in the design.

The issues are not located inside the EMIF but within the IP.

Maybe you can relocate the pll to closer location to the EMIF IP.

Also you can run the compilation with the High Effort and maybe try with different seed.


It's not much I can help you in term of this.

The timing specialist can help you to close the timing.


Thanks,

Adzim


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