HalloThis is my first project with Altera. I am using the quatras 2 synthesis tool and simulink to generate a design for my FPGA. But when i try to synthesis the code i get the following error can't determine definition of operator ""srl"" i tried google, but did not get a clear explanation. What i understood is srl is a command to shift right logically. Can any one please explain me in details what is the cause of this problem?
Hallo TrickyThanks for the quick reply. Here is my Matlab function for a CIC filter. I get the error on the line where i cast the x. I am not sure if the next parts of the code will also produce some error. function y = CIC4FPGA( x ) % 4th order CIC filter with 2 times oversampling % over = cast(2,'int32'); x = cast(x/8,'int32'); % this line shows the error persistent comb integrator if isempty( comb ) comb = cast(zeros(4,1),'int32'); integrator = cast(zeros(4,1),'int32'); end xx= cast(zeros(length(x)*over, 1),'int32'); y = cast(zeros(length(x)*over, 1),'int32'); a = cast(0,'int32'); b = cast(0,'int32'); % Calculate Comb stage for i = 1:length(x) a = x(i) - comb(1); comb(1) = x(i); b = a - comb(2); comb(2) = a; a = b - comb(3); comb(3) = b; b = a - comb(4); comb(4) = a; xx( 2*( i-1) + 1 ) = b; % insert (over - 1) zeros end; for i=1:length(xx) integrator(1) = integrator(1) + xx(i); integrator(2) = integrator(2) + integrator(1); integrator(3) = integrator(3) + integrator(2); integrator(4) = integrator(4) + integrator(3); y(i) = integrator(4); end;
The matlab code is not causing the error. I assume you're using hdl coder to generate the hdl for quartus. Can you post this code? And what version of matlab is it?
Yes i am using HDL coder from Simulink. I have MATALB 2014. The setup i have is a like the attached image. I make a subsytem out of the FIR interpolation filter and the CIC function. I am also attaching the CIC filter HDL code that i generate. I get the error at line 92 of the CIC filter file. If you need i can upload you the whole Simulink file and my function block.
For some reason it is trying to shift a real, which is not possible. You need to convert all of your code to use fixed point numbers, not floating, because floating will not be synthesisable.
Yes i know that floating point is not synthesisable. That's why i convert my variables to 'int32' using the cast command. MATLAB treats 'int32' as a fixed point (1,32,0) in this format. So i guess this is not the problem. But any idea for which loop or some structure in my code it tries to shift a real? I really did not understand the part 'it is trying to shift a real'. can you please clear this error, so i can pass it to my boss and maybe he has an idea
Move the cast external to the code that is converted to hdl. Do not have any floating point in any code that will be converted to hdl. Have all inputs as int 32 type.
HalloSo did a change in the MATLAB code and it complets the logic synthesis now. i changed the x to x = bitshift(x,-3) %bitshift is a builting MATLAB function My next question is to perform mapping is it necessary to have the device connected to the pc? I still dont have a development board from ALTERA. Can i post the questions with the mapping later on this thread or should i ask it on a new thread?
Up to you were you post. You will need the board connected via jtag value to program it. As for data it depends what methods you are using to send the data. If its all via matlab it may have ethernet support. But I you may need to contact mathworks or a matlab forum for support.