Can't execute the assertion debug on tutorial

[YuukiSU]

Hello from Japan,

I tried the assertion debug tutorial (page 197, Chapter 15 in Questa Tutorial PDF) with tutorial files.

/<install_dir>/examples/tutorials/systemverilog/vlog_dut

But, I couldn't execute this tutorial because of the errors.

# ** Error: Failure to checkout svverification license feature.
# ** Error: (vsim-1) Unable to checkout verification license - required for testbench features (randomize, randcase, randsequence, covergroup).
#    Time: 0 ns  Iteration: 0  Instance: /top File: top.sv

I serched about the error and found this topic about svverification license.
Questa Intel Edition licensing 

I added -nocvg option to all vsim commands in assert.do file and tried the tutorial, but I haven't been able to execute with these errors.

# ** Warning: (vsim-3394) Covergroup object construction is disabled because of '-nocvg' switch. As a result, any hierarchical access of covergroup/coverpoint/cross option variable in a procedural context will crash.
#    Time: 0 ns  Iteration: 0  Region: /top/dut/sm_transitions_cvg File: interleaver.sv
# ** Error: Failure to checkout svverification license feature.
# ** Error: (vsim-1) Unable to checkout verification license - required for testbench features (randomize, randcase, randsequence, covergroup).
#    Time: 0 ns  Iteration: 0  Instance: /top File: top.sv

To my understanding, the assertion feature is enable for Questa-Intel FPGA Edition (including Starter Edition).

Can I solve these problems?

Thanks,

[RichardTanSY_Intel]

I can't seem to solve this issue. I will need to consult this issue with the engineering team.

Siemen Questasim seems to work (not Intel FPGA Edition). You may use it as a workaround.

Best Regards,

Richard Tan

[YuukiSU]

I'm an assertion beginner so I continue to study it.

I'm looking forward to hear a good news about this issue.

Best Regards,
YuukiSU

[RichardTanSY_Intel]

As it turns out, this is a limitation in Questa Intel FPGA Edition. It does not support simulating advanced verification features as mentioned in the error message (randomize, randcase, randsequence, covergroup).

You may need to use Questasim if you want to simulate advanced verification features.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.

[YuukiSU]

I think "-nocvg" option disable these advanced verification features (rondomize, randcase, randsequence and covergroup), also I think the SystemVerilog Asertion feature w/o these advanced verification features is enable in Questa-Intel FPGA Edition. Are these right?

Best Regards,
YuukiSU

[RichardTanSY_Intel]

Simulating with vsim -nocvg disables covergroup object construction and removes the ability to run built-in covergroup methods during simulation. An svverification license is not required when -nocvg is used in the simulation.

Unfortunately, the Questa* - Intel® FPGA Edition simulator does not support SystemVerilog assertions as well.

Best Regards,

Richard Tan

[YuukiSU]

I watched the debug demo video in the Questa-Intel FPGA Edition introduction page.
In this video, the engineer introduces about "Assertion Debug" from 3:43.
Questa*-Intel® FPGA Edition Debug Demo 

Also, it is mentioned about assertion support in the video about migration from Modelsim Intel FPGA Edition to Questa Intel FPGA Edition.
I paste the snapshot of these videos.

Are these introductions wrong?

Best Regards,
YuukiSU

[RichardTanSY_Intel]

My bad. I confirm with the engineering team that Questa Intel FPGA Edition does support SV assertions.

Yesterday, I found from a document that it mentioned Questa does not support SV assertion but the information is not correct.

Best Regards,

Richard Tan

[YuukiSU]

Thank you for your confirmation.

After all, I can execute the SV assertion but can't some features which need svverification license, right?

Best Regards,
YuukiSU

[RichardTanSY_Intel · Accepted solution]

We should remove/disable any testbench features that require advanced verification licenses.

Coverage related code (which requires advanced verification licenses) can be disabled using vsim command option -nocvg.

Best Regards,

Richard Tan

[YuukiSU]

I understand.

If there will be some questions, I want to post newly. 

Thank you for your kind supports.

Best Regards,

YuukiSU

[RichardTanSY_Intel]

Thanks for acknowledge the solution provided. 

 I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you on your follow-up questions.

Thank you.

Best Regards,

Richard Tan

p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 9/10 survey.