I have created a platform designer based design (Quartus 20.1.1) that includes the SDRAM controller. I am attempting to run a simulation using Modelsim Intel-Edition, and keep hitting this error:
# ** Error (suppressible): (vsim-8885) Illegal inout port connection for port 'DRAM_DQ' to reg type.
The code and testbench are written in systemverilog, the DQ port of the SDRAM controller is defined as inout. I tried adding the logic keyword to the port declaration with no change.
Any assistance greatly appreciated.
I ran verror 8885 at the Modelsim prompt, see this:
# vsim Message # 8885:
# Only nets can be connected to inout ports.
# A variable data type is not permitted on either side of an inout port.
# [DOC: IEEE Std 1800-2012 System Verilog LRM - 23.3.3.2 Port connection rules for variables]
#
# This message will be downgraded to a warning with the -permissive argument.
# This error message can be suppressed or downgraded to a note or warning.
I cannot find any information on the -permissive argument, what is it an argument to? Trying to use it with vsim results in errors.
Any assistance greatly appreciated.
Cheers, Randy R
