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Altera_Forum
Honored Contributor I
1,299 Views

Can't instantiate Signal Tap using megafunction tool in Quartus 17.0.1

I am attempting to instantiate a signal tap core using the megafunction flow. Quartus generates the IP but when I instantiate it in my project and compile I get the following error. 

 

Error(13785): VHDL Use Clause error at signal_tap.vhd(47): design library "altera_signaltap_ii_logic_analyzer_170" does not contain primary unit "sld_signaltap"  

 

It works fine using .stp files but this approach doesn't fit into the flow that I'm attempting to use.
0 Kudos
13 Replies
Altera_Forum
Honored Contributor I
172 Views

Can you show your code? The message implies an issue with your instantiation or the libraries you've pointed to with USE.

Altera_Forum
Honored Contributor I
172 Views

Here is my code. I don't think it has anything to do with the instantiation because if I generate the IP as a Verilog module things work. Why do I get this error generating the IP core in VHDL? 

 

 

 

library IEEE; 

use IEEE.STD_LOGIC_1164.ALL; 

use IEEE.NUMERIC_STD.ALL; 

 

 

entity adder_top is 

port( 

clock : in std_logic; 

resetn : in std_logic; 

 

oready : out std_logic; 

ivalid : in std_logic; 

idata : in std_logic_vector(31 downto 0); 

 

ovalid : out std_logic; 

iready : in std_logic; 

odout : out std_logic_vector(31 downto 0) 

 

); 

end adder_top; 

 

architecture Behavioral of adder_top is 

 

 

 

 

component signal_tap is 

port ( 

acq_clk : in std_logic := 'X'; -- clk 

acq_data_in : in std_logic_vector(63 downto 0) := (others => 'X'); -- acq_data_in 

acq_trigger_in : in std_logic_vector(0 downto 0) := (others => 'X') -- acq_trigger_in 

); 

end component signal_tap; 

 

signal s_sum : unsigned(32 downto 0); 

signal s_trigger : std_logic_vector(0 downto 0); 

 

begin 

 

ovalid <= '1';  

odout <= std_logic_vector(s_sum(31 downto 0)); 

oready <= '1'; 

s_trigger(0) <= ivalid; 

 

process(clock) 

begin 

if rising_edge(clock) then 

if (resetn='0') then 

s_sum <= (others=>'0'); 

else 

s_sum <= s_sum + X"00000001"; 

end if; 

end if; 

end process; 

 

 

signal_tap_inst : component signal_tap 

port map ( 

acq_clk => clock,  

acq_data_in => idata(31 downto 0) & std_logic_vector(s_sum(31 downto 0)),  

acq_trigger_in => s_trigger  

); 

 

end Behavioral;
Altera_Forum
Honored Contributor I
172 Views

Hi, 

 

You need to add in the signal tap in the IP catalog, I attached the example for your in Q17.0.1std version. 

 

Thanks 

Kentan 

(This message was posted on behalf of Intel Corporation)
Altera_Forum
Honored Contributor I
172 Views

For one thing, your instantiation is incorrect. You have the word "component" in there. It should just be: 

 

signal_tap_inst: signal_tap port map ( 

 

What happens when you remove "component"?
Altera_Forum
Honored Contributor I
172 Views

 

--- Quote Start ---  

For one thing, your instantiation is incorrect. You have the word "component" in there. It should just be: 

 

signal_tap_inst: signal_tap port map ( 

 

What happens when you remove "component"? 

--- Quote End ---  

 

 

 

Yes, you had to remove the component. Even though Quartus does not error on this.
SDe_J
Novice
172 Views

I having this same error in quartus 18.0, and the suggestions here have not solved it. Is there anything else I should try?

sstrell
Honored Contributor II
172 Views

We'd have to see your code.

SDe_J
Novice
172 Views

Attached is my code. I followed the tips posted here, but I get these errors:

Error(13785): VHDL Use Clause error at signaltap.vhd(47): design library "altera_signaltap_ii_logic_analyzer_180" does not contain primary unit "sld_signaltap" Error(13827): Ignored construct rtl at signaltap.vhd(76) due to previous errors Error(13806): VHDL syntax error at stratix10Test_top.vhd(44) near text ; Error(13806): VHDL syntax error at stratix10Test_top.vhd(51) near text variable Error(13806): VHDL syntax error at stratix10Test_top.vhd(57) near text elsif Error(13806): VHDL syntax error at stratix10Test_top.vhd(59) near text if Error(13806): VHDL syntax error at stratix10Test_top.vhd(61) near text if Error(13806): VHDL syntax error at stratix10Test_top.vhd(69) near text if Error(13806): VHDL syntax error at stratix10Test_top.vhd(71) near text if Error: Flow failed: Error: Quartus Prime Synthesis was unsuccessful. 10 errors, 0 warnings Error: Peak virtual memory: 1137 megabytes Error: Processing ended: Wed Feb 6 14:40:56 2019 Error: Elapsed time: 00:00:12 Error: Total CPU time (on all processors): 00:00:12

I think the 'Error (13806)' messages are from quartus not knowing what to do after the signaltap instance fails.

 

Strangely, I get this error if the signaltap .ip file is included in the quartus project, even if it's not instantiated in the top module..

SDe_J
Novice
172 Views

Here is my signaltap .ip file

 

 

sstrell
Honored Contributor II
172 Views

Did you enable Signal Tap and point to your .stp file in the Settings dialog box (Assignment menu)?

SDe_J
Novice
172 Views

Do I need to do that if I'm using the signaltap ip file instead of the GUI signaltap?

 

I still get this error if I enable signaltap in the settings.

sstrell
Honored Contributor II
172 Views

Always. You still need a .stp file for control. That's why, in most cases, it doesn't make sense to use the Signal Tap IP instantiation flow because you need the .stp file anyway.

SDe_J
Novice
172 Views

Ah. I was hoping to use this as a workaround, since I can't get signaltap to work at all (as in my other post: https://forums.intel.com/s/question/0D50P00004DnM9wSAF/signaltap-problem-with-stratix-10-production-...)

 

Thanks,

-Sam

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