Can't open msim.vcd

[sher1ock]

I'm having a problem running a simulation for school. I found someone with the exact same problem Here but the solution they found was linked to another forum that is now gone so I don't know how they fixed it. 

My problem is that every time I run a simulation it tries to run and then I get:

Reading /home/chrx/intelFPGA_lite/20.1/assignments/sevenseg/Waveform.vwf...

Reading /home/chrx/intelFPGA_lite/20.1/assignments/sevenseg/simulation/qsim/sevensegment.msim.vcd...

Unable to open /home/chrx/intelFPGA_lite/20.1/assignments/sevenseg/simulation/qsim/sevensegment.msim.vcd 

Error. 

The sim worked the first time I ever tried it on another project, but never again. 
I've since reinstalled twice since then with no change. 

I've checked and the file is there, but the only thing it contains is: 

#1000000

Here's the VWF from the simulation in case that's helpful:

/*<simulation_settings>
<ftestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off sevensegment -c sevensegment --vector_source="/home/chrx/intelFPGA_lite/20.1/assignments/sevenseg/Waveform.vwf" --testbench_file="/home/chrx/intelFPGA_lite/20.1/assignments/sevenseg/simulation/qsim/Waveform.vwf.vt"</ftestbench_cmd>
<ttestbench_cmd>quartus_eda --gen_testbench --tool=modelsim_oem --format=verilog --write_settings_files=off sevensegment -c sevensegment --vector_source="/home/chrx/intelFPGA_lite/20.1/assignments/sevenseg/Waveform.vwf" --testbench_file="/home/chrx/intelFPGA_lite/20.1/assignments/sevenseg/simulation/qsim/Waveform.vwf.vt"</ttestbench_cmd>
<fnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=on --flatten_buses=off --tool=modelsim_oem --format=verilog --output_directory="/home/chrx/intelFPGA_lite/20.1/assignments/sevenseg/simulation/qsim/" sevensegment -c sevensegment</fnetlist_cmd>
<tnetlist_cmd>quartus_eda --write_settings_files=off --simulation --functional=off --flatten_buses=off --timescale=1ps --tool=modelsim_oem --format=verilog --output_directory="/home/chrx/intelFPGA_lite/20.1/assignments/sevenseg/simulation/qsim/" sevensegment -c sevensegment</tnetlist_cmd>
<modelsim_script>onerror {exit -code 1}
vlib work
vlog -work work sevensegment.vo
vlog -work work Waveform.vwf.vt
vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.sevensegment_vlg_vec_tst
vcd file -direction sevensegment.msim.vcd
vcd add -internal sevensegment_vlg_vec_tst/*
vcd add -internal sevensegment_vlg_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script>
<modelsim_script_timing>onerror {exit -code 1}
vlib work
vlog -work work sevensegment.vo
vlog -work work Waveform.vwf.vt
vsim -novopt -c -t 1ps -L fiftyfivenm_ver -L altera_ver -L altera_mf_ver -L 220model_ver -L sgate_ver -L altera_lnsim_ver work.sevensegment_vlg_vec_tst
vcd file -direction sevensegment.msim.vcd
vcd add -internal sevensegment_vlg_vec_tst/*
vcd add -internal sevensegment_vlg_vec_tst/i1/*
proc simTimestamp {} {
echo "Simulation time: $::now ps"
if { [string equal running [runStatus]] } {
after 2500 simTimestamp
}
}
after 2500 simTimestamp
run -all
quit -f
</modelsim_script_timing>
<hdl_lang>verilog</hdl_lang>
</simulation_settings>*/
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/

/*
Copyright (C) 2020 Intel Corporation. All rights reserved.
Your use of Intel Corporation's design tools, logic functions 
and other software and tools, and any partner logic 
functions, and any output files from any of the foregoing 
(including device programming or simulation files), and any 
associated documentation or information are expressly subject 
to the terms and conditions of the Intel Program License 
Subscription Agreement, the Intel Quartus Prime License Agreement,
the Intel FPGA IP License Agreement, or other applicable license
agreement, including, without limitation, that your use is for
the sole purpose of programming logic devices manufactured by
Intel and sold by Intel or its authorized distributors. Please
refer to the applicable agreement for further details, at
https://fpgasoftware.intel.com/eula.
*/

HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 0.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}

SIGNAL("I1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}

SIGNAL("I2")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}

SIGNAL("O1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}

TRANSITION_LIST("I1")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 100;
LEVEL 0 FOR 5.0;
LEVEL 1 FOR 5.0;
}
}
}

TRANSITION_LIST("I2")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 50;
LEVEL 0 FOR 10.0;
LEVEL 1 FOR 10.0;
}
}
}

TRANSITION_LIST("O1")
{
NODE
{
REPEAT = 1;
LEVEL X FOR 1000.0;
}
}

DISPLAY_LINE
{
CHANNEL = "I1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}

DISPLAY_LINE
{
CHANNEL = "I2";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}

DISPLAY_LINE
{
CHANNEL = "O1";
EXPAND_STATUS = COLLAPSED;
RADIX = Binary;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}

TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

[sstrell]

I'm not sure if this is the issue, but try putting your projects and other files where there are no dots or spaces in the path name.  I know ModelSim and QuestaSim don't like spaces.  Not sure about dots.

[sher1ock]

I tried that already and I just tried again. No luck. 

[sstrell]

The top lines in your file are pointing to ModelSim instead of Questa and show Verilog as the HDL instead of VHDL.  Perhaps you have some settings wrong in Quartus for generating these files.

[sher1ock]

I'm using modelsim though. 

[sstrell]

Well, something is mixed up somewhere because there's a mix of ModelSim and QuestaSim paths for some reason and a reference to Verilog even though you are using VHDL.

[sher1ock · Accepted solution]

Thank you! This gave me a place to start looking. Problem was with the settings in the initial setup wizard. It was set to use veralog with modelsim.

[Paveetirra_Srie]

I’m glad that your question has been addressed, I now transition this thread to community support. 

If you have a new question, feel free to open a new thread to get the support from Intel experts.

Otherwise, the community users will continue to help you on this thread. 

Thank you.