Can't verify DDR2 Controller timing ... Missing quartus_tan.exe ?

[Altera_Forum]

Hi, 

 I made DDR2 controller for Cyclone II using Megafunction wizard in Quartus II 12.0. I am unable to build the testbed example the megafunction creates. It appears to compile the design, but then fails while running the "auto_verify_ddr_timing.tcl" script. The key error message seems to be:   couldn't execute "c:\altera\12.0\quartus\bin\quartus_tan": no such file or directory   Indeed, there is no quartus_tan.exe file in my quartus distribution. After searching, it sounds like quartus_tan is the old timing analysis program. So, I guess they don't supply it any longer.    So, why does the megafunction use old (non existing) timing analyzer? How should I run the verification script? I can configure the wizard to not perform the timing verification and it does complete the build then, but it seems like a bad idea to me not to run the verification.    What do you think? Should I just bypass the verification script? Can anyone point me to where the quartus_tan.exe program is? Should I try to modify the scripts to use the newer analyzer?    I appreciate any suggestions. A bit more of the message log is below.   Thanks, Ryan   P.S. I also had the same problem with Quartus II 11.1       Info: Command: quartus_sh -t auto_verify_ddr_timing.tcl compile fpga_1_1_pretest fpga_1_1_pretest Info: Quartus(args): compile fpga_1_1_pretest fpga_1_1_pretest Info:  Info: ======================================================= Info: == DDR/DDR2-SDRAM Megacore 12.0 In-System Timing Verification  Info: ======================================================= Info:  Info: Verifying in-system timing for DDR/DDR2-SDRAM Megacore variation 'ddr2' Info:  Info: Running Quartus II Timing Analyzer (delay extraction only) Info: See file 'ddr2_extraction_log.txt' for detailed log messages Info: Running Timing Analysis using tan_arg2.tcl Info: couldn't execute "c:\altera\12.0\quartus\bin\quartus_tan": no such file or directory Error: Post compile timing analysis failed (retcode=1) Info: The most likely cause of this type of error is: Info: (1) Some signals on the local-side interface are not connected causing logic to be optimised away, Info: This script requires that the complete logic for the specified width of the datapath (both read and write paths) be present in the design. Info: (2) The clear-text HDL files for the datapath may have been modified. Info: (3) Not all clocks from the system pll are global. Info: Postcompile not run Info: In-System timing verification of DDR/DDR2-SDRAM Megacore variation 'ddr2' complete. Info: Please run the appropriate script for In-System verification of other DDR/DDR2-SDRAM Megacore variations you may have in your project, and check system Fmax. Error (23031): Evaluation of Tcl script auto_verify_ddr_timing.tcl unsuccessful Error: Quartus II 32-bit Shell was unsuccessful. 2 errors, 0 warnings Error: Peak virtual memory: 127 megabytes Error: Processing ended: Mon Sep 03 08:01:00 2012 Error: Elapsed time: 00:00:01 Error: Total CPU time (on all processors): 00:00:01 Error (293001): Quartus II Full Compilation was unsuccessful. 4 errors, 42 warnings