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Can we drive QSFP reference clock using an internal clock generated from a PLL

Desani
Beginner
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While driving the reference clock(322.2 MHz) to 10G ethernet mac interface, I am prompted with the error below,

Error(18957): Signal u1|iopll_0|stratix10_altera_iopll_i|outclk[0] is constrained to be routed locally to port REF_IQCLK on destination dut_inst|atx_pll_inst|xcvr_atx_pll_s10_htile_0|ct1_hssi_pma_lc_refclk_select_mux_inst, but this signal must be routed through the global network

 

Tried using the constraint 

set_instance_assignment -name GLOBAL_SIGNAL GLOBAL_CLOCK -to "u1:inst|iopll_0|stratix10_altera_iopll_i|outclk[0]" -entity altera_eth_top

 

to make the PLL output global but still fails to compile.

 

I am generating the ref_clk_clk using a PLL, is this not allowed?

 

How do I resolve the issue? Any help is appreciated.

 

Thanks

Raam

Desani_0-1649840561780.png

 

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Ash_R_Intel
Employee
645 Views

Hi,


I found one KDB article similar to the error message that you are getting.

https://www.intel.in/content/www/in/en/support/programmable/articles/000086844.html?wapkw=Error(18957)%20signal%20must%20be%20routed%20through%20the%20global%20network


Can you confirm if it is applicable to you and the Quartus version is matching for you?


Regards


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Ash_R_Intel
Employee
643 Views

Hi,

As the example design that you are using use this refclk to drive the ATX and fPLL both, their corresponding restrictions apply. For ATX PLL, the restriction is as mentioned in the below document:


https://www.intel.com/content/www/us/en/docs/programmable/683621/current/atx-pll.html


The input reference clock can be driven from one of the following sources. The sources are listed in order of performance, with the first choice giving the highest performance.

  • Dedicated reference clock pin
  • Reference clock network (with two new high quality reference clock lines)
  • Receiver input pin

The input reference clock is a differential signal. Intel® recommends using the dedicated reference clock pin as the input reference clock source for the best jitter performance. The input reference clock must be stable and free-running at device power-up for proper PLL operation and PLL calibration. If the reference clock is not available at device power-up, then you must recalibrate the PLL when the reference clock is available.


This explains the error that you are getting.


Regards


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