Can we specify cut timing path along with the code?

Altera_Forum · ‎06-13-2013

Hello,

I have a toggle synchronizer like below and want to exclude the domain crossing register transfer ce_t1 <= ce_toggle from timing analysis. Is there any way to do it automatically, e.g. by a synthesis attribute or a script, without picking up individual code instances after synthesis?

Best regards,

Frank

   PROCESS (ce)
   BEGIN
      IF rising_edge(ce) THEN
         ce_toggle <= NOT ce_toggle;
      END IF;
   END PROCESS;
   PROCESS (clk)
   BEGIN
      IF rising_edge(clk) THEN
         ce_t1 <= ce_toggle;
         ce_t2 <= ce_t1;
         ce_s <= ce_t1 XOR ce_t2;
      END IF;
   END PROCESS;

Altera_Forum · ‎06-13-2013

This what I found in the QII13.0 help:

--- Quote Start ---

The following example shows how you can also use altera_attribute for more complex assignments involving more than one instance. In this example, the following VHDL sample uses an altera_attribute to cut all timing paths from q1 to q2:

signal q1, q2 : std_logic;

attribute altera_attribute : string;

-- Equiv to set_instance_assignment -name CUT ON -from q1 -to q2

attribute altera_attribute of q1 : signal is "-name CUT ON -to q2";

You may specify either the -to option or the -from option in a single altera_attribute; integrated synthesis automatically sets the remaining option to the target of the altera_attribute. You may also specify wildcards for either option. For example, if you specify * for the -to option instead of q2, the Quartus II software cuts all timing paths from q1 to every other register in the design.

--- Quote End ---

Wouldn't you need an extra register stage before applying the xor to get the output pulse?

Regards,

Josy

Altera_Forum · ‎06-13-2013

--- Quote Start ---

Wouldn't you need an extra register stage before applying the xor to get the output pulse?

--- Quote End ---

Possibly, depending on the intended metastable event probability. But the point stands besides my question.

Regrads,

Frank

Altera_Forum · ‎06-13-2013

Sorry for being a bit pedantic on the synch-chain.

But did the quote from the 'QII 13.0 Help' help?

Regards,

Josy

Altera_Forum · ‎06-13-2013

--- Quote Start ---

This what I found in the QII13.0 help:

Wouldn't you need an extra register stage before applying the xor to get the output pulse?

Regards,

Josy

--- Quote End ---

Yes Josy I will drive xor only after two stages as the signals are assumed synchronised from that node onwards.

FvM approach is one stage and is sampling to xor from first synchroniser register. This will fail more frequently than two stage.

Since you found the cut path attribute then it means it exists and hopefully still active.

Altera_Forum · ‎06-13-2013

I'm quite sure it still exists for AHDL code (e.g. dcfifo).

I expect it to exist for Verilog (as this is Altera's 'new' default language), so I don't see why they wouldn't support it for VHDL.

Regards,

Josy

Altera_Forum · ‎06-14-2013

--- Quote Start ---

Sorry for being a bit pedantic on the synch-chain.

But did the quote from the 'QII 13.0 Help' help?

--- Quote End ---

I apologize for my inobservance. Somehow I overlooked the quote in your post. Yes, the attribute solves the problem.

I mean to have searched the Quartus Software Handbook before, but ended up with the impression that the signal specification in the attribute must provide a full node name as in the respective tcl or qsf statement. But this isn't the case and to achieve there are enough examples to see how it works.

You are also right that standard metastability MTBF requires double registering before the XOR. In the specific application, one register level has been spared to achieve lower delay, because a certain failure rate (getting zero or double output pulses) can be accepted in this case. But I won't suggest it generally.

Thanks,

Frank

Altera_Forum · ‎10-30-2013

Hi Frank,

Would you please share your code in which you are able to cut the timings between two nodes?

I want to cut the timing between two nodes same as in your example.Following is my code

reg wptr;

(* altera_attribute = "-name CUT on -from wptr" *) reg rq1_wptr;

reg rq2_wptr;

always @(posedge clk or negedge rst_n)

if(~rst_n)

{rq2_wptr,rq1_wptr} <= {1'b0,1'b0};

else

{rq2_wptr,rq1_wptr} <= {rq1_wptr,wptr};

Thanks,

Krupesh

Altera_Forum · ‎11-11-2013

Rysc has provided me the solution. You can find the solution from the following link

http://www.alteraforum.com/forum/showthread.php?t=42805&p=177061#post177061

Thanks,

Krupesh