Can you explain why the 3 "arriav" libraries are not listed in library mapping file for VCS, the synopsys_sim.setup that is generated under /simulation/scsim ?

[ARach7]

Test-case:​

$QUARTUS_ROOTDIR/qdesigns/binary_cam. 

At EDA simulation library compiler, choose CycloneV and arriav and compile the in Verilog.

At the synopsys_sim.setup file created for the example at /simulation/scsim, the 3 arriav* libraries ( arriav_ver, arriav_hssi_ver, arriav_pcie_hip_ver ) are not listed  .

You may say - these are different families, and I will reply:

Some of the cells listed at  synopsys_sim.setup  requires modules that were compiled into arriav* libraries, for example: cell altera_arriav_pll

that was parsed to library ALTERA_LNSIM_VER.

Now, since arriav* libraries are not listed, we end up with plenty of unresolved module errors over real design.

[ARach7]

​To complete the example above from $QUARTUS_ROOTDIR/qdesigns/binary_cam, add to the project files the below tb.v file as testbench, and instruct the tool to compile it (assignements->settings-> EDA Tool settings-> simulation: "Compile Testbench".

%cat tb.v

`timescale 1ps/1ps

module tb();

binary_cam_wrapper u_binary_cam_wrapper ();

      altera_arriav_pll       altera_arriav_pll ();

endmodule

Error: Error: VCS MX: Error-[URMI] Unresolved modules

Error: Error: VCS MX: "arriav_ffpll_reconfig #(.P_XCLKIN_MUX_SO_0__PLL_CLKIN_0_SRC(local_pll_clkin_0_src_0), .P_XCLKIN_MUX_SO_0__PLL_CLKIN_1_SRC(local_pll_clkin_1_src_0), .P_XCLKIN_MUX_SO_0__PLL_CLK_SW_DLY(local_pll_clk_sw_dly_0), .P_XCLKIN_MUX_SO_0__PLL_CLK_SW_DLY_SETTING(local_pll_clk_sw_dly_0), .P_XCLKIN_MUX_SO_0__PLL_MANU_CLK_SW_EN(local_pll_manu_clk_sw_en_0), .P_XCLKIN_MUX_SO_0__PLL_AUTO_CLK_SW_EN(local_pll_auto_clk_sw_en_0), .P_XCLKIN_MUX_SO_0__PLL_CLK_LOSS_SW_EN(local_pll_clk_loss_sw_en_0), .P_XCLKIN_MUX_SO_1__PLL_CLKIN_0_SRC(local_pll_clkin_0_src_1), .P_XCLKIN_MUX_SO_1__PLL_CLKIN_1_SRC(local_pll_clkin_1_src_1), .P_XCLKIN_MUX_SO_1__PLL_CLK_SW_DLY(local_pll_clk_sw_dly_1), .P_XCLKIN_MUX_SO_1__PLL_CLK_SW_DLY_SETTING(local_pll_clk_sw_dly_1), .P_XCLKIN_MUX_SO_1__PLL_MANU_CL ... "

Error: Error: VCS MX:  Module definition of above instance is not found in the design.

[Deshi_Intel]

Hi, Can you help me to understand more on the problem statement ? 1) Which Quartus version that you are using ? 2) Which VCS MX version that you are using ? 3) And this sim error issue is impacting which Intel FPGA IP ? Arria V fpll IP ? 4) How can I duplicate this sim error issue ? Is there some example design that I can use or you will be able to share your sim design project here ? Thanks. Regards, dlim

[ARach7]

Using Quartus 18.1 Using VCS 2017.12. It’s a general question: what will trigger Quartus scripts to add arriav* logical libraries (arriav_hssi_ver, arriav_ver, arriav_pcie_hip_ver) into synopsys_sim.setup? Suppose my testbench file (that is added to project file using “compile testbench”) has an instance of “altera_arriav_pll”. That “altera_arriav_pll” cell will needs staff from arriav, but these libraries are not found in synopsys_sim.setup, although they were compiled with EDA simulation library compiler. thanks

[Deshi_Intel]

HI,

I have generated a simple Arria V Transceiver PLL IP core. A sim project folder will be generated as well . Attached is the IP sim folder.

You can find the script "vcsmx_setup.sh" that call out the Arria V library in following path.

• AV_PLL_sim\synopsys\vcsmx

Thanks.

Regards,

dlim