Can you force synthesis of registers?

[SparkyNZ]

bit [ 11 : 0 ] colorRGB[ 7 : 0 ];
bit [ 11 : 0 ] tempRGB;
..
tempRGB = colorRGB[ dataH ];
..
dataR = tempRGB[ 11 : 8 ];

When the above  code is synthesized, tempRGB does not appear in the RTL Viewer. It has been optimized/removed from the synthesized design.

Is there a way to force Quartus into synthesizing registers? ie. Is there a keyword I can use so that tempRGB must appear in my design?

[ak6dn]

It is critical to understand the difference between blocking (=) and non-blocking (<=) assignments.

Blocking assignments work just like, for example, programming in C with assignments. So:

B = A;
C = B;
D = C;

at the end D will have whatever value A had in it. Computations and assignments strictly follow sequentially.

However, in a non-blocking sequence:

B <= A;
C <= B;
D <= C;

each right hand side gets evaluated with the current values of the variables, but no assignment is performed. Once all right hand sides are evaluated, then, at the end of the event block, all the computed right hand sides are stored in the corresponding left hand sides.

So the above sequence will take 3 time states to propagate the initial value in A to the final register D.