Cannot drive PLL from a altclkctrl block

[A_Meerbann]

I am working on a MAX10 10M50 device with Quartus Prime lite 2021.1.0

My design uses an external IO pin as a clock source. This pin is NOT a dedicatd clock pin.

I instantiated a altclkctrl bock to route this pin to the global clock resource. The output of that block is connected to the input of a PLL.

Still I get en error telling me that the PLL cannot be placed because it's input is not connected to a non-inverted input pin, another PLL or a clock control block. Then it states that it is driven by a clock control block:

Warning (15899): PLL "pll:pll_1|altpll:altpll_component|pll_altpll:auto_generated|pll1" has parameters clk0_multiply_by and clk0_divide_by specified but port CLK[0] is not connected
Error (15065): Clock input port inclk[0] of PLL "pll:pll_1|altpll:altpll_component|pll_altpll:auto_generated|pll1" must be driven by a non-inverted input pin or another PLL, optionally through a Clock Control block
Info (15024): Input port INCLK[0] of node "pll:pll_1|altpll:altpll_component|pll_altpll:auto_generated|pll1" is driven by clkctrl:clkctrl_1|clkctrl_altclkctrl_0:altclkctrl_0|clkctrl_altclkctrl_0_sub:clkctrl_altclkctrl_0_sub_component|wire_clkctrl1_outclk which is OUTCLK output port of Clock control block type node clkctrl:clkctrl_1|clkctrl_altclkctrl_0:altclkctrl_0|clkctrl_altclkctrl_0_sub:clkctrl_altclkctrl_0_sub_component|clkctrl1

So what's wrong here? How can I make this work?

[sstrell]

Can you show your code and how you've made the connections?  The warning about CLK[0] not being connected could be part of the issue.

[Ash_R_Intel]

The ALTCLKCTRL block inclk signal has following restriction:

Clock pins, clock outputs from the PLL, and core signals can drive the inclk[] port.

Reference: https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/max-10/ug_m10_clkpll.pdf#page=51, Table 14

The input clock of the ALTCLKCTRL should be driven by a dedicated clock input pin and not just any IO pin.

Regards

[Ash_R_Intel]

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