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Altera_Forum
Honored Contributor I
751 Views

Cannot run stimulus module using Quartus Prime?

Attempting to learn Verilog right now. I am currently running through Verilog HDL by Palanatkir and am using Quartus Prime Lite as my current EDA. I am very new at this but just wondering, the book has us code a stimulus block as one of our very first exercises. I cannot figure out how to get Quartus to compile with it, as Quartus just states that the top level block has no logic. 

 

Here is my code: 

 

module stimulus; reg clk; reg reset; wire q; R_CC rcc0(q, clk, reset); initial clk = 1'b0; // set clk to 0 always # 5 clk = ~clk; // toggle clk every 5 tu initial begin reset = 1'b1; # 15 reset = 1'b0; # 180 reset = 1'b1; # 10 reset = 1'b0; # 20 $finish; // terminate sim end initial $monitor($time, " Output q = %d", q); endmodule // module - basic building block of Verilog // Ripple Carry Counter module R_CC(q, clk, reset); output q; // io signal and vector decl input clk, reset; T_FF tff0(q, clk, reset); T_FF tff1(q, q, reset); T_FF tff2(q, q, reset); T_FF tff3(q, q, reset); endmodule module T_FF (q, clk, reset); output q; input clk, reset; wire d; D_FF dff0(q, d, clk, reset); not nl(d, q); // not is a Verilog primative endmodule module D_FF(q, d, clk, reset); output q; input d, clk, reset; reg q; // wtf always @(posedge reset or negedge clk) if (reset) q <= 1'b0; else q <= d; endmodule 

 

Maybe I am using the wrong tool? Should I be using ModelSim or something similar?
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4 Replies
Altera_Forum
Honored Contributor I
32 Views

This is a testbench, and intended to be run in a simulator. Quartus is a tool for compiling code for FPGAs, and not a proper simulator (it does have a very basic simulator, but it doesnt understand testbenches properly) 

This code needs to be ruin in something like Modelsim
Altera_Forum
Honored Contributor I
32 Views

Thank you!

Altera_Forum
Honored Contributor I
32 Views

RTL that you can implement in the FPGA needs to be "synthesizable" So in the code above things like# and $monitor do not map to hardware resources that are inside the FPGA and are provided in the language for the reasons Tricky said. If you google "synthesizable verilog" you'll find a lot of topics on this to help you identify what parts are synthesizable and which are simulation only. In Quartus there are a bunch of templates you can refer to which should all be synthesizable, with a verilog file open in Quartus go to Edit --> Insert Template and navigate to the verilog templates to see examples of how you code various synthesizable blocks.

Altera_Forum
Honored Contributor I
32 Views

Hey I forgot to read this at the time (and I think I missed it) because school had started to ramp up and this brick wall kind of discouraged me but, I just started to get back to studying Verilog on my own. 

 

I actually had the exact same problem and ended up google searching back to my original question and this helped so much. Verilog templates are great examples and explain a lot. 

 

Appreciate it so much.
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