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Cannot simulate ALTRCLKCTRL

Altera_Forum
Honored Contributor II
‎11-29-2016 06:43 PM
1,386 Views

Hello everyone, 

 

I am trying to use ALTCLKCTRL IP in my design. The project compiles just fine, but when I try to simulate it using ModelSim (using NativeLink feature in Quartus II 16.0), I get the following errors: 

# Loading altclkctrl_0.clk_gate_altclkctrl_0_sub# ** Error (suppressible): (vsim-10000) C:/EPCQ_update/core/clk_gate/simulation/submodules/clk_gate_altclkctrl_0.v(56): Unresolved defparam reference to 'sd1' in sd1.clock_type.# Time: 0 ps Iteration: 0 Instance: /tb_epcq_update/UUT/dclk_gate/altclkctrl_0/clk_gate_altclkctrl_0_sub_component File: C:/EPCQ_update/core/clk_gate/simulation/submodules/clk_gate_altclkctrl_0.v# ** Error (suppressible): (vsim-10000) C:/EPCQ_update/core/clk_gate/simulation/submodules/clk_gate_altclkctrl_0.v(57): Unresolved defparam reference to 'sd1' in sd1.ena_register_mode.# Time: 0 ps Iteration: 0 Instance: /tb_epcq_update/UUT/dclk_gate/altclkctrl_0/clk_gate_altclkctrl_0_sub_component File: C:/EPCQ_update/core/clk_gate/simulation/submodules/clk_gate_altclkctrl_0.v# ** Error (suppressible): (vsim-10000) C:/EPCQ_update/core/clk_gate/simulation/submodules/clk_gate_altclkctrl_0.v(58): Unresolved defparam reference to 'sd1' in sd1.lpm_type.# Time: 0 ps Iteration: 0 Instance: /tb_epcq_update/UUT/dclk_gate/altclkctrl_0/clk_gate_altclkctrl_0_sub_component File: C:/EPCQ_update/core/clk_gate/simulation/submodules/clk_gate_altclkctrl_0.v# Error loading design 

 

Did anyone try using ALTCLKCTRL IP and had any success simulating the block. Any help is appreciated. 

 

Thanks, 

Yev
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Altera_Forum
Honored Contributor II
‎01-17-2017 11:45 PM
387 Views

Hi Yev, 

 

Did you resolve this problem? I'm having the same issue using Quartus Prime Lite Edition. 

 

Regards, 

 

Steve
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Altera_Forum
Honored Contributor II
‎01-17-2017 11:57 PM
387 Views

Hi Steve, 

 

Apparently, there is a bug that prevents Quartus to auto-generate a good working .v file for simulation. I did not have time chasing the problem, but instead abstracted out the block for simulation. 

 

Yev
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Altera_Forum
Honored Contributor II
‎01-18-2017 12:50 AM
387 Views

Hi Yev, 

 

Many thanks for your reply. I will not waste any more time trying to chase this issue but will do what you did and remove the module for simulation. 

 

Steve
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