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Altera_Forum
Honored Contributor I
761 Views

Cannot the parameters list be empty in SystemVerilog?

Hi All, 

 

What's the problem with the following code?  

 

pmu# () i_pmu (// Outputs .clk0 (clk_mn), // Inputs .rstn_ext (rstn_ext), .clk_ext (clk_ext));  

 

Cannot the parameters list be empty? I'm receiving the "Error (10170): Verilog HDL syntax error at amp_top.v(272) near text: ")"; expecting ".", or an operand". Why? 

 

Thank you!
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Altera_Forum
Honored Contributor I
36 Views

Quartus doesn't tolerate empty parameter lists, no. 

 

Cheers, 

Alex