Capturing Signals with SignalTap using a "burst" clock

[SparkyNZ]

Rather than using a continuous clock cycle (such as the bottom signal shown below), I have a signal (clkDebug) which follows the clock in bursts. The reason I have done this is that I don't have enough storage space to sample/store all of the regular clock pulses in between.

So, I have confirmed with SignalTap that my clkDebug signal is behaving as expected. Unfortunately I cannot get SignalTap to trigger and record any data when I use clkDebug.

If I switch to my regular clk, it does trigger.

Does SignalTap have some limitation in that it cannot use a clock that only operates in bursts?

UPDATE:

Or.. is it actually triggering but not showing me the data because insufficient clock samples have occurred? As you can see below, it has actually triggered but it sits on "Acquiring post-trigger data".

[SparkyNZ · Accepted solution]

I have confirmed what was happening. SignalTap was triggering but it was waiting for it's buffer to fill up before it would stop.

I modified my design to let the clkDebug run continuously once I had captured the states of interest (which fills the buffer) and I get what I was after.

[sstrell]

A better solution would be to use a continuous clock for triggering and use the storage qualification feature to have the tool only store the samples in the buffer you want/need.  There are a number of storage qualification options you can use.

And yes, as you found, if the buffer does not fill up completely on its own, the logic analyzer continues to run until it does fill or you manually stop it, at which point you can see data in the partially full buffer.  So your trigger did occur.