Hallo
For my design i am using Simulink and HDL coder from MATLAB to generate the HDL code. Then i use the Altera Quatras II to synthesize and generate the programming file for my DE0-NANO development kit board with cyclone V (EP4CE22F17C6).
I am trying to make an interpolation filter of 256 Up sampling. But this is too big for the HDL coder to generate the code. To solve that problem i used one interpolation filter with 32 up sample and other one with 8 up sample. Then i cascaded the two filters to get the desired 256 up sampling. Now the problem starts with Restricted Fmax when i try to generate the HDL code for this model. When i generate HDL code for 32 up sample and 8 up sample separately without cascading them together both of them have a Fmax around 50 MHz. But when i cascade them and generate the HDL code for the model the Fmax comes down to 35 MHz. Whats is the reason behind this? Is there any optimization i can apply to increase the Fmax. I know clock optimization will increase the area, but that's now an concern right now.
