HalloFor my design i am using Simulink and HDL coder from MATLAB to generate the HDL code. Then i use the Altera Quatras II to synthesize and generate the programming file for my DE0-NANO development kit board with cyclone V (EP4CE22F17C6). I am trying to make an interpolation filter of 256 Up sampling. But this is too big for the HDL coder to generate the code. To solve that problem i used one interpolation filter with 32 up sample and other one with 8 up sample. Then i cascaded the two filters to get the desired 256 up sampling. Now the problem starts with Restricted Fmax when i try to generate the HDL code for this model. When i generate HDL code for 32 up sample and 8 up sample separately without cascading them together both of them have a Fmax around 50 MHz. But when i cascade them and generate the HDL code for the model the Fmax comes down to 35 MHz. Whats is the reason behind this? Is there any optimization i can apply to increase the Fmax. I know clock optimization will increase the area, but that's now an concern right now.
This is likely a design issue. Have you got plenty of delay blocks breaking up your pipeline? 50Mhz seems rather slow, I would expect 150Mhz+ for a well pipelined design.
I completely agree with you, and i also think that this might be a design issue. I did add some pipeline through simulink hdl coder. But as you suggested that did not really help that much. Any suggestion on can i properly utilize the pipeline. I can give you the simulink file that i am using for you to have a look.
This should not be a math issue. I think you adders are too wide to operate in one clock cycle. In a current Cyclone 4 I have a CIC4-Fiter working at 100 MHz, but it has to be pipelined in 5 stages.