Clock PLL error

[UMall1]

I use a PLL in my FPGA - EP3C80F484C6N. I am receiving the following warning from Quartus.

Warning (15899): PLL "SENSOR_CLOCK:U_SENSOR_CLOCK|altpll:altpll_component|SENSOR_CLOCK_altpll:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK[1] is not connected

What does this message mean? I simulate the module and see that all derived clocks are present and correct.

Udayan Mallik

[ak6dn]

Quartus detects that you entered some configuration parameters for the CLK[1] output but you don't actually use CLK[1].

It's a WARNING, you can ignore it.

[Ash_R_Intel]

Hi,

This Warning is received when the output of the PLL is unconnected. Refer the Quartus Help link below:

https://www.intel.com/content/www/us/en/programmable/quartushelp/21.3/index.htm#msgs/msgs/wcut_pll_mult_div_specified_clock_not_connected.htm

Regards