I use a PLL in my FPGA - EP3C80F484C6N. I am receiving the following warning from Quartus.
Warning (15899): PLL "SENSOR_CLOCK:U_SENSOR_CLOCK|altpll:altpll_component|SENSOR_CLOCK_altpll:auto_generated|pll1" has parameters clk1_multiply_by and clk1_divide_by specified but port CLK is not connected
What does this message mean? I simulate the module and see that all derived clocks are present and correct.
This Warning is received when the output of the PLL is unconnected. Refer the Quartus Help link below: