Intel® Quartus® Prime Software
Intel® Quartus® Prime Design Software, Design Entry, Synthesis, Simulation, Verification, Timing Analysis, System Design (Platform Designer, formerly Qsys)
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Clock Skew reported from transceiver PHY to user logic

Honored Contributor II

Hello Experts, I need your help. 

I have a simple UDP offload design (10G using two ethernet ports). I have two flavours of Stratix V GX FPGAs, an A7 and an AB (5SGXEABK2H40C2). When I build the design on the A7 FPGA, it builds fine and meets timing comfortably. However when I build it on the AB it has problems, namely within the Ethernet controller - specifically between the TX MAC portion and the PHY. The TimeQuest timing reports a setup violation on the TX clock/path. The negative slack is very minute around -0.06. The recommendation points towards clock skew and asks me to use global clock resources (currently using periphery resources via ALTCLKCTRL) for the source and destination clock. I tried using Global and Regional and the results was much worse. The problem I have is that the MAC portion is hidden third party IP so cannot modify. So I am wondering what to do? 


I have tried the following: 

- tried changing to global/regional clock 

- tried all types of optimisations within the fitter settings and including aggressive performace 

- tried locking logic closer to the PHY 


Nothing has improved it by much. Any ideas would help. 


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